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freescale semiconductor data sheet: advance information document number: mpc5675k rev. 4, 04/2011 ? freescale semiconductor, inc., 2009?2011. all rights reserved. preliminary?subject to change without notice this document contains information on a prod uct under development. freescale reserves the right to change or discontinue this product without notice. mpc5675k tbd mapbga?225 15 mm x 15 mm qfn12 ##_mm_x_##mm sot-343r ##_mm_x_##mm pkg-tbd ## mm x ## mm 257 mapbga (14 x 14 mm) 473 mapbga (19 x 19 mm) 1 overview this document provides electrical specifications, pin assignments, and package diagrams for the mpc5675k series of mi crocontroller units (mcus). the mpc5675k microcontroller is a 32-bit embedded controller design ed for advanced driver assistance systems with radar, cmos imaging, lidar and ultrasonic sensors, and multiple 3-phase motor control applications as in hybrid electric vehicles (hev) in automotive and high temperature industrial applications. a member of freescale semiconductor?s mpc5500/5600 family, it contains the book e compliant power architecture ? technology core with variable length encoding (vle). this core complies with the power architecture embedded category, and is 100 percen t user mode compatible with the original power pc ? user instruction set architecture (uisa). it offers system performance up to four times that of its mpc5561 predecessor, while bringing you the reliab ility and familiarity of the proven power ar chitecture technology. a comprehensive suite of hardware and software development tools is availa ble to help simplify and speed system design. development support is available from leading tools vendors providing compilers, debuggers and simulation development environments. mpc5675k microcontroller data sheet 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3 feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.4 feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 package pinouts and signal descriptions . . . . . . . . . . . . . . . . 23 2.1 package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3 electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . 73 3.3 recommended operating conditions . . . . . . . . . . . . . . 75 3.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 77 3.5 electromagnetic interference (emi) characteristics . . . 79 3.6 electrostatic discharge (esd) characteristics. . . . . . . . 79 3.7 static latch-up (lu). . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 3.8 power management controller (pmc) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 3.9 supply current characteristics . . . . . . . . . . . . . . . . . . . 82 3.10 temperature sensor electrical characteristics . . . . . . . 83 3.11 main oscillator electrical characteristics . . . . . . . . . . . . 83 3.12 fmpll electrical characteristics. . . . . . . . . . . . . . . . . . 84 3.13 16 mhz rc oscillator electrical characteristics . . . . . . 85 3.14 adc electrical characteristics. . . . . . . . . . . . . . . . . . . . 85 3.15 flash memory electrical characteristics . . . . . . . . . . . . 91 3.16 sram memory electrical characteristics . . . . . . . . . . . 93 3.17 gp pads specifications . . . . . . . . . . . . . . . . . . . . . . . . . 93 3.18 pdi pads specifications . . . . . . . . . . . . . . . . . . . . . . . . 95 3.19 dram pad specifications . . . . . . . . . . . . . . . . . . . . . . 100 3.20 reset characteristics . . . . . . . . . . . . . . . . . . . . . . . . 106 3.21 reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 3.22 peripheral timing characteristics. . . . . . . . . . . . . . . . . 114 4 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 4.1 package mechanical data. . . . . . . . . . . . . . . . . . . . . . 136 5 orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 6 reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 7 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . 143
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice overview freescale semiconductor 2 1.1 device comparison table 1. mpc5675k family device comparison features MPC5673K mpc5674k mpc5675k cpu type 2 e200z7d (sor 1 ) in lock-step or decoupled operation architecture harvard execution speed 0?150 mhz (+2% fm) 0?180 mhz (+2% fm) 0?180 mhz (+2% fm) nominal platform frequency (in 1:1, 1:2, and 1:3 modes) 0?75 mhz (+2% fm) 0?90 mhz (+2% fm) 0?90 mhz (+2% fm) mmu 64 entries (sor) instruction set ppc yes instruction set vle yes instruction cache 16 kb, 4-way with edc (sor) data cache 16 kb, 4-way with edc (sor) mpu yes (sor) buses core bus 32-bit address, 64-bit data internal periphery bus 32-bit address, 32-bit data xbar master ? slave ports yes (sor) memory static ram (sram) 256 kb (ecc) 384 kb (ecc) 512 kb (ecc) code flash memory 1mb 2 1.5 mb 2 2mb 2 data flash memory 64 kb 2 modules analog-to-digital converter (adc) 257 pin pkg: 4 12 bit (22 external channels) 473 pin pkg: 4 12 bit (up to 34 external channels) crc unit 2 (3 contexts each) cross triggering unit (ctu) 2 modules deserial serial peripheral interface (dspi) 2 modules (3 chip selects) 3 modules (3 chip selects) digital i/os ? 16 dram controller (dramc) no yes 3 enhanced direct memory access (edma) 2 modules, 32 channels each etimer 3 modules, 6 channels each
overview mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 3 modules (cont.) external bus interface (ebi) 1 module 3 16-bit data + address or 32-bit data with address bus muxed 4 fast ethernet controller (fec) 1 module fault collection and control unit (fccu) 1 module flexcan 4 modules (32 message buffers each) flexpwm 3 modules (each 4 3 channels) flexray optional i 2 c 2 modules 3 modules interrupt controller (intc) yes (sor) linflex 3 modules 4 modules parallel data interface (pdi) 1 module 4 periodic interrupt timer (pit) 1 module, 4 channels software watchdog timer (swt) yes (sor) system timer module (stm) yes (sor) temperature sensor 1 module wakeup unit (wkpu) yes crossbar switch (xbar) 3 modules, 2 are user-configurable clocking clock monitor unit (cmu) 3 modules clock output 2 modules frequency-modulated phase-locked loop (fmpll) 2 modules (system and auxiliary) ircosc ? 16 mhz 1 xosc 4 mhz ? 40 mhz 1 supply power management unit (pmu) yes 1.2 v low-voltage detector (lvd12) 1 1.2 v high-voltage detector (hvd12) 1 2.7 v low-voltage detector (lvd27) 4 table 1. mpc5675k family device comparison (continued) features MPC5673K mpc5674k mpc5675k
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice overview freescale semiconductor 4 debug nexus class 3+ (for cores and sram ports) packages mapbga 257 pins 473 pins temperature ambient see the t a recommended operating condition in the device data sheet notes: 1 sphere of replication. 2 does not include test or shadow flash memory space. 3 available only on 473-pin package. 4 ddr available only on 473 package. other modules available as follows: ebi or ddr on 473 package. ebi + pdi on 473 package. ddr + pdi on 473 package pdi only on 257 package. table 1. mpc5675k family device comparison (continued) features MPC5673K mpc5674k mpc5675k
overview mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 5 1.2 block diagram figure 1 shows a top-level block di agram of the mpc5675k device. figure 1. mpc5675k block diagram dma_1 adc ? analog-to-digital converter bam ? boot assist module cmu ? clock monitoring unit crc ? cyclic redundanc y check unit ctu ? cross triggering unit dspi ? deserial serial peripheral interface ebi ? external bus interface ecc ? error correction code ecsm ? error correction status module edma ? enhanced direct memory access controller fccu ? fault collection and control unit fec ? fast ethernet controller flexcan ? controller area network controller flexpwm ? pulse width modulator module fmpll ? frequency-modulated phase-locked loop i 2 c ? inter-integrated circuit controller intc ? interrupt controller ircosc ? internal rc oscillator jtag ? joint test action group interface mc ? mode entry, clock, reset, & power modules mddr ? mobile double data rate dynamic ram pbridge ? peripheral bridge pdi ? parallel data interface pit ? periodic interrupt timer pmu ? power management unit rc ? redundancy checker rtc ? real time clock sema4 ? semaphore unit siul ? system integration unit lite sscm ? system status and configuration module stm ? system timer module swt ? software watchdog timer tsens ? temperature sensor xosc ? crystal oscillator ecsm_0 stm intc crossbar switch (xbar_2) mmu d-cache e200z7d e200z7d crossbar switch (xbar_1) memory protection unit pbridge jtag nexus flexray pbridge siul mc wakeup adc adc xosc bam sscm secondary pll fmpll ircosc cmu cmu ctu pit fccu flexpwm flexpwm etimer etimer etimer flexcan flexcan linflex linflex dspi dspi dspi crc cmu sema4 tsens pdi adc adc ctu flexpwm linflex linflex flexcan flexcan mddr i 2 c i 2 c i 2 c crc crossbar switch (xbar_0) core_0 core_1 i-cache dma_0 fec pflashc pflashc rc ecsm_1 stm intc sema4 rc sram with ecc logic rc rc rc ebi sram with ecc logic memory protection unit pbridge mmu d-cache i-cache
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice overview freescale semiconductor 6 1.3 feature list ? high-performance e200z7d dual core ? 32-bit power architecture ? technology cpu ? up to 180 mhz core frequency ? dual-issue core ? variable length encoding (vle) ? memory management unit (mmu) with 64 entries ? 16 kb instruction cache and 16 kb data cache ? memory available ? up to 2 mb code flash memory with ecc ? 64 kb data flash memory with ecc ? up to 512 kb on-chip sram with ecc ? sil3/asild innovative safety concept: lockstep mode and fail-safe protection ? sphere of replication (sor) for key components ? redundancy checking units on outputs of the sor connected to fccu ? fault collection and control unit (fccu) ? boot-time built-in self-test for memory (mbi st) and logic (lbist) triggered by hardware ? boot-time built-in self-tes t for adc and flash memory ? replicated safety-enhanced watchdog timer ? junction temperature sensor ? non-maskable interrupt (nmi) ? 16-region memory protection unit (mpu) ? clock monitoring units (cmu) ? power management unit (pmu) ? cyclic redundancy check (crc) units ? decoupled parallel mode for high-pe rformance use of replicated cores ? nexus class 3+ interface ? interrupts ? replicated 16-priority interrupt controller ? replicated 32-channel edma controller ? gpios individually programmable as input, output, or special function ? three general-purpose etimer units (6 channels each) ? three flexpwm units with four 16-bit channels per module ? communications interfaces ? 4 linflex modules ? 3 dspi modules with automa tic chip select generation ? 4 flexcan interfaces (2.0b ac tive) with 32 message objects
overview mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 7 ? flexray module (v2.1) with dual channel, up to 128 messag e objects and up to 10 mbit/s ? fast ethernet controller (fec) ?3 i 2 c modules ? four 12-bit analog-to-dig ital converters (adcs) ? 22 input channels ? programmable cross triggering unit (ctu) to synchronize adc conversion with timer and pwm ? external bus interface ? 16-bit external ddr memory controller ? parallel digital interface (pdi) ? on-chip can/uart bootstrap loader ? capable of operating on a single 3.3 v voltage supply ? 3.3 v-only modules: i/o, oscillators, flash memory ? 3.3 v or 5 v modules: adcs, supply to internal vreg ? 1.8?3.3 v supply range: dram/pdi ? operating junction temperature range ?40 to 150 c 1.4 feature details 1.4.1 high-performance e2 00z7d core processor ? dual 32-bit power architecture ? processor core ? loose or tight core coupling ? freescale variable length encoding (vle) en hancements for code size footprint reduction ? thirty-two 64-bit genera l-purpose registers (gprs) ? memory management unit (mmu) with 64-entry fu lly-associative transl ation look-aside buffer (tlb) ? branch processing unit ? fully pipelined load/store unit ? 16 kb instruction and 16 kb data caches per core with line locking ? four way set associative ? two 32-bit fetches per clock ? eight-entry store buffer ? way locking ? supports tag and data parity ? vectored interrupt support ? signal processing engine 2 (spe2) auxiliary processing un it (apu) operating on 64-bit general purpose registers
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice overview freescale semiconductor 8 ? floating point ?ieee ? 754 compatible with software wrapper ? single precision in hardware; double precision with so ftware library ? conversion instructions between single precision floating point and fixed point ? long cycle time instructions (except for guarded lo ads) do not increase interrupt latency in the mpc5675k ? to reduce latency, long cycle time instru ctions are aborted upon interrupt requests ? extensive system developmen t support through nexus debug module 1.4.2 crossbar switch (xbar) ? 32-bit address bus, 64-bit data bus ? simultaneous accesses from differen t masters to different slaves (t here is no clock penalty when a parked master accesses a slave) 1.4.3 memory protection unit (mpu) the memory protection unit splits the physical me mory into 16 different regions. each master (dma, flexray, cpu) can be assigned di fferent access rights to each region. ? 16-region mpu with concurrent ch ecks against each master access ? 32-byte granularity for protected address region 1.4.4 enhanced direct memo ry access (edma) controller ? 32 channels support independent 8-, 16-, 32-bit single value or block transfers ? supports variable-sized que ues and circular queues ? source and destination address regi sters are independently configured to post-increment or remain constant ? each transfer is initiated by a peri pheral, cpu, or edma channel request ? each edma channel can optionally send an interr upt request to the cpu on completion of a single value or block transfer 1.4.5 interrupt controller (intc) ? 208 peripheral interrupt requests ? 8 software settable sources ? unique 9-bit vector per interrupt source ? 16 priority levels with fixed hardware arbitrati on within priority levels for each interrupt source ? priority elevation for shared resources
overview mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 9 1.4.6 frequency-modulated ph ase-locked loop (fmpll) two fmplls are available on each device. each fmpll allows the user to gene rate high speed system clocks st arting from a minimum reference of 4 mhz input clock. further, the fmpll supports programmable freque ncy modulation of the system clock. the pll multiplication factor and output clock divider ratio are software configurable. the fmplls have the following major features: ? input frequency: 4?40 mhz continuous ra nge (limited by the crystal oscillator) ? voltage controlled oscillator (vco) range: 256?512 mhz ? frequency modulation via so ftware control to reduce and control emission peaks ? modulation depth 2% if centere d or 0% to ?4% if downshifted via software control register ? modulation frequency: triangular modulation with 25 khz nominal rate ? option to switch modulation on and off via software interface ? reduced frequency divider (rfd) for re duced frequency operation without re-lock ? 2 modes of operation ? normal pll mode with cr ystal reference (default) ? normal pll mode with external reference ? lock monitor circuitry with lock status ? loss-of-lock detection for re ference and feedback clocks ? self-clocked mode (scm) operation ? auxiliary fmpll ? used for flexray due to precise symb ol rate requirement by the protocol ? used for motor control periphery and connected ip (a/d digital inte rface ctu) to allow independent frequencies of operation for pwm and timers as well as jitter-free control ? option to enable/disable modulation to avoid protocol violation on jit ter and/or potential unadjusted error in elect ric motor control loop ? allows running motor control periphery at differ ent (precisely lower, equal, or higher ,as required) frequency than the system to ensure higher resolution 1.4.7 external bus interface (ebi) ? available on 473-pin devices ? data and address options: ? 16-bit data and address (non-muxed) ? 32-bit data and address (bus-muxed) ? mpc5561 324 bga compatibility mode: 16-bit data bus, 24-bit address bus is default addr[8:31], but configurable to 26-bit address bus. ? memory controller with sup port for various memory types ? non-burst and burst mode sdr flash and sram ? asynchronous/legacy flash and sram
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice overview freescale semiconductor 10 ? configurable bus speed modes ? support for 2 mb address space ? chip select and write/byte en able options as presented in the pin-muxing table in section 2, package pinouts and signal descriptions ? configurable wait states (via chip selects) ? optional automatic clkout gating to save power and reduce emi 1.4.8 on-chip flash memory ? up to 2 mb code flash memory with ecc ? 64 kb data flash memory with ecc ? censorship protection scheme to prevent flash content visibility ? multiple block sizes to support features such as boot block, ope rating system block, and eeprom emulation ? read-while-write with multiple partitions ? parallel programming mode to suppor t rapid end of line programming ? hardware programming state machine 1.4.9 cache memory ? harvard architecture cache ? 16 kb instruction / 16 kb data ? four-way set-associative harvard (instruction and data) 256-bit long cache ? two 32-bit fetches per clock ? eight-entry store buffer ? way locking ? supports tag and data parity 1.4.10 on-chip internal static ram (sram) ? up to 512 kb general-purpose sram ? ecc performs single-bit corr ection, double-bit error detection ? address included in ecc checkbase 1.4.11 dram controller the dram controller (ava ilable only on 473-pin devices) is a mult i-port controller that monitors incoming requests on the three ahb slave ports and decides (at each rising clock edge) what command needs to be sent to the external dram. the dram controller on this device supp orts the following types of memories: ? mobile ddr (mddr)
overview mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 11 ? ddr 1 ? ddr 2 (optional) ?sdr the controller has th e following features: ? optimized timing for 32-byte bursts a nd single read accesses on the ahb interface ? optimized timing for 8-byte and 16-byte bursts on the dramc interface ? supports priority elevation on the slave ports for single accesses ? 16-bit wide dram interface ? one chip select (cs) ? mddr memory controller ? 16-bit external interface ? address range up to 8 mb 1.4.12 boot assist module (bam) ? enables booting via serial mode (flexcan, linflex) ? handles static mode in case of an erroneous boot procedure ? implemented in 8 kb rom ? supports lock step mode (lsm) and decoupled parallel mode (dpm) 1.4.13 parallel data interface (pdi) ? support for external adc and cmos image sensors ? parallel interface operation up to mcu system bus frequency ? selectable data capture fr om rising or falling edge ? receive fifo with adjust able trigger thresholds ? data width for 8, 10, 12, 14, and 16 bits ? data packing unit to pack input data on 64-bit words ? data packed on 8- or 16- bit boundary, depending on input data width ? binary increasing channel select that allows as many as eight cha nnels to be selected ? frame synchronization th rough vsync, hsync, pixclk 1.4.14 deserial serial peripher al interface (dspi) modules ? three serial peripheral interfaces ? full duplex communication ports with interrupt and edma request support ? support for all functional modes from q spi submodule of qsmcm (mpc5xx family) ? support for queues in ram ? six chip selects, expandable to 64 with external demultiplexers ? programmable frame size, baud rate, clock de lay, and clock phase on a per-frame basis
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice overview freescale semiconductor 12 ? modified spi mode for interfacing to peri pherals with longer setup time requirements ? support for up to 60 mbit/s in slave only rx mode 1.4.15 serial communication interface module (linflex) the linflex on this device features the following: ? supports lin master mode, lin slave mode, and uart mode ? lin state machine compliant to lin1.3, 2.0, and 2.1 specifications ? manages lin frame transmission a nd reception without cpu intervention ? lin features ? autonomous lin frame handling ? message buffer to store as many as 8 data bytes ? supports messages as long as 64 bytes ? detection and flagging of lin er rors (sync field, delimiter, id parity, bit framing, checksum and time-out errors) ? classic or extended checksum calculation ? configurable break duration of up to 36-bit times ? programmable baud rate prescalers (13-bit mantissa, 4-bit fractional) ? diagnostic features (loop back, li n bus stuck dominant detection) ? interrupt-driven operation with 16 interrupt sources ? lin slave mode features ? autonomous lin header handling ? autonomous lin response handling ? uart mode ? full-duplex operation ? standard non return-to-zero (nrz) mark/space format ? data buffers with 4-byte receive, 4-byte transmit ? configurable word length (8-b it, 9-bit, or 16-bit words) ? configurable parity scheme: none, odd, even, always 0 ? speed as fast as 2 mbit/s ? error detection and flagging (parity, noise, and framing errors) ? interrupt-driven operation wi th four interrupt sources ? separate transmitter and r eceiver cpu interrupt sources ? 16-bit programmable baud-rate modul us counter and 16-bit fractional ? two receiver wake-up methods ? support for dma-enabled transfers
overview mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 13 1.4.16 flexcan ? thirty-two message buffers each ? full implementation of the can pr otocol specification, version 2.0b ? programmable acceptance filters ? individual rx filtering per message buffer ? short latency time for high priority transmit messages ? arbitration scheme according to me ssage id or message buffer number ? listen-only mode capabilities ? programmable clock source: syst em clock or oscillator clock ? reception queue possible by sett ing more than one rx message buffer with the same id ? backwards compatible with previous flexcan modules ? safety can features on 1 can m odule as implemented on mpc5604p 1.4.17 dual-channel flexray controller ? full implementation of flex ray protocol specification 2.1 ? sixty-four configurable me ssage buffers can be handled ? message buffers configurab le as tx, rx, or rxfifo ? message buffer size configurable ? message filtering for all messa ge buffers based on frameid, cycle count, and message id ? programmable acceptance filters for rxfifo message buffers ? dual channel, each at up to 10 mbit/s data rate 1.4.18 periodic interrupt timer (pit) the pit module implements the features below: ? four general-purpose interrupt timers ? 32-bit counter resolution ? clocked by system clock frequency ? 32-bit counter for real time interrupt, clocked from main external oscillator ? can be used for software tick or dma trigger operation 1.4.19 system timer module (stm) the stm implements the features below: ? duplicated periphery to guarantee that safety targets (sil3) are achieved ? up-counter with four output compare registers ? os task protection and hardware tick implemen tation as per current st ate-of-the-art autosar requirement
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice overview freescale semiconductor 14 1.4.20 motor control (motc) peripherals the peripherals in this section can be used for gene ral-purpose applications, but are specifically designed for motor control (motc) applications. 1.4.20.1 flexpwm the pulse width modulator module (flexpwm) cont ains three pwm channels, each of which is configured to control a single half -bridge power stage. there may also be one or more fault channels. this pwm is capable of controlling most motor t ypes: ac induction motors (acim), permanent magnet ac motors (pmac), both brushless (bldc) and brush dc motors (bdc ), switched (srm) and variable reluctance motors (vrm), and stepper motors. a flexpwm module implements the following features: ? 16 bits of resolution for center, edge aligned, and asymmetrical pwms ? maximum operating frequency lower than or equal to platform frequency ? clock source not modulated a nd independent from system cloc k (generated via auxiliary pll) ? fine granularity control for enha nced resolution of the pwm period ? pwm outputs can operate as compleme ntary pairs or independent channels ? ability to accept signed numbers for pwm generation ? independent control of both edges of each pwm output ? synchronization to external hard ware or other pwm is supported ? double-buffered pwm registers ? integral reload rates from 1 to 16 ? half-cycle reload capability ? multiple adc trigger events can be generated per pwm cycle via hardware ? fault inputs can be assigned to control multiple pwm outputs ? programmable filters for fault inputs ? independently programmable pwm output polarity ? independent top and botto m deadtime insertion ? each complementary pair can operate with its own pwm frequency and deadtime values ? individual software control for each pwm output ? all outputs can be forced to a value simultaneously ? pwmx pin can optionally output a third signal from each channel ? channels not used for pwm generation can be used for buffered output compare functions ? channels not used for pwm generation ca n be used for input capture functions ? enhanced dual-edge capture functionality ? option to supply the source for each complement ary pwm signal pair from any of the following: ? external digital pin ? internal timer channel
overview mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 15 ? external adc input, taking into account valu es set in adc high and low limit registers ? dma support 1.4.20.2 cross triggering unit (ctu) the ctu provides automatic generati on of adc conversion re quests on user selected conditions without cpu load during the pwm period and with mi nimized cpu load for dynamic configuration. the ctu implements the following features: ? cross triggering between adc, flex pwm, etimer, and external pins ? double-buffered trigger generation uni t with as many as eight independent triggers generated from external triggers ? maximum operating frequency lowe r than or equal to platform ? trigger generation unit configurable in sequential mode or in triggered mode ? trigger delay unit to compensate th e delay of external low-pass filter ? double-buffered global trigger unit allowing etimer synchroni zation and/or adc command generation ? double-buffered adc command list point ers to minimize adc-trigger unit update ? double-buffered adc conversion command list with as many as twenty-four adc commands ? each trigger has the capability to generate consecutive commands ? adc conversion command allows controlli ng adc channel from each adc, single or synchronous sampling, independent result queue selection ? dma support with safety features 1.4.20.3 analog-to-digital converter (adc) ? four independent adcs wi th 12-bit a/d resolution ? common mode conversion range of 0?5 v or 0?3.3 v ? twenty-two single-ended input channels ? supports eight fifo queues with fixed priority ? queue modes with priority-based preemption; init iated by software command, internal, or external triggers ? dma and interrupt request support 1.4.20.4 etimer module three 16-bit general purpose up/dow n timer/counters per module are im plemented with the following features: ? ability to operate up to platform frequency ? individual channel capability ? input capture trigger ? output compare
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice overview freescale semiconductor 16 ? double buffer (to capture rising edge and falling edge) ? separate prescaler for each counter ? selectable clock source ? 0?100% pulse measurement ? rotation direction flag (quad decoder mode) ? maximum count rate ? equals peripheral clock/2 for external event counting ? equals peripheral clock for internal clock counting ? cascadeable counters ? programmable count modulo ? quadrature dec ode capabilities ? counters can share available input pins ? count once or repeatedly ? preloadable counters ? pins available as gpio when timer functionality not in use ? dma support 1.4.21 redundancy control and checker unit (rccu) the rccu checks all outputs of the sphere of replicat ion (addresses, data, cont rol signals). it has the following features: ? duplicated module to guarantee highest possi ble diagnostic coverage (check of checker) ? replicated ip to be used as checkers on th e pbridge output, flash controller output, sram output, dma channel mux inputs 1.4.22 software watchdog timer (swt) this module implements the features below: ? duplicated periphery to guarantee that safety targets (sil3) are achieved ? fault-tolerant output ? safe internal rc oscillator as reference clock ? windowed watchdog ? program flow control monitor with 16-bit pseudorandom key generation ? allows high level of safety (sil3 monitor) 1.4.23 fault collection an d control unit (fccu) the fccu module has the following features: ? redundant collection of hardware checker results ? redundant collection of error information and latc h of faults from critic al modules on the device
overview mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 17 ? collection of test results ? configurable and graded fault control ? internal reactions (no internal reaction, nmi, reset, or safe mode) ? external reaction (failure is reported to the outside world via confi gurable output pins) 1.4.24 system integration unit lite (siul) the siul controls mcu re set configuration, pad configuration, ex ternal interrupt, general purpose i/o (gpio), internal peripheral multiplexing, and the sy stem reset operation. the reset configuration block contains the external pin boot configuration logic. the pa d configuration block contro ls the static electrical characteristics of i/o pins . the gpio block provides uniform and di screte input/output control of the i/o pins of the mcu. the siul provides the following features: ? centralized pad control on per-pin basis ? pin function selection ? configurable weak pullup/pulldown ? configurable slew rate c ontrol (slow/medium/fast) ? hysteresis on gpio pins ? configurable automatic safe mode pad control ? input filtering for external interrupts 1.4.25 cyclic redundan cy checker (crc) unit the crc module is a configurable mu ltiple data flow unit to compute crc signature s on data written to an input register. the crc unit has the following features: ? three sets of register s to allow three concurrent cont exts with possibl y different crc computations, each with a se lectable polynomial and seed ? computes 16- or 32-bit wide crc on the fly (single-cycle computation) and stores the result in an internal register ? implements the following standard crc polynomials: ? x 16 + x 12 + x 5 + 1 [16-bit crc-ccitt] ? x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 [32-bit crc-ethernet(32)] ? key engine to be coupled with communication periphery where crc application is added to allow implementation of safe communication protocol ? offloads the core from cycle-consuming crc a nd helps in checking the configuration signature for safe start-up or periodic procedures ? connected as a peripheral on the internal peripheral bus ? provides dma support
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice overview freescale semiconductor 18 1.4.26 non-maskable interrupt (nmi) the non-maskable interrupt with de-gli tching filter is available to suppo rt high priority core exceptions. 1.4.27 system status and co nfiguration module (sscm) the sscm on the mpc5675k features the following: ? system configuration and status ? debug port status and debug port enable ? multiple boot code starting locati ons out of reset through implemen tation of search for valid reset configuration half word ? sets up the mmu to allow user boot code to execute as either clas sic powerpc book e code (default) or as freescale vle code out of flash ? supports serial bootloading of either classic po werpc book e code (default) or freescale vle code ? detection of user boot code ? automatic switch to serial boot mode if internal flash is blank or invalid 1.4.28 nexus development interface (ndi) ? per ieee-isto 5001-2008 ? real-time development support fo r power architecture core thr ough nexus class 3 (some class 4 support) ? nexus support to snoop system sram traffic ? data trace of flexray accesses ? read and write access ? configured via the ieee 1149.1 (jtag) port ? high bandwidth mode for fast message transmission ? reduced bandwidth mode for reduced pin usage 1.4.29 ieee 1149.1 jtag controller (jtagc) ? ieee 1149.1-2001 test access port (tap) interface ? jcomp input that provides the ability to shar e the tap ?selectable modes of operation include jtagc/debug or normal system operation ? 5-bit instruction register that sup ports ieee 1149.1-2001 defi ned instructions ? 5-bit instruction register that su pports additional publ ic instructions ? three test data registers: ? bypass register ? boundary scan register ? device identifi cation register ? tap controller state machine that controls the ope ration of the data register s, instruction register, and associated circuitry
package pinouts and signal descriptions mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 19 2 package pinouts and signal descriptions 2.1 package pinouts figure 2 shows the mpc5675k in the 257 mapbga package. figure 3 through figure 6 show the mpc5675k in the 473 mapbga package. figure 2. mpc5675k 257 mapbga pinout (top view) 1234567891011121314151617 a vss_ hv_io vss_ hv_io vdd_ hv_io nexus mdo[5] nexus mdo[7] nexus mdo[9] flexray cb_tx flexray ca_tr_ en vdd_ hv_io fec rxd[2] fec rx_ clk fec rxd[0] fec mdio fec tx_en fec txd[3] vss_ hv_io vss_ hv_io a b vss_ hv_io vss_ hv_io mc_cgl clk_out can1 txd nexus mdo [14] dspi2 cs1 flexray cb_tr_ en flexray ca_tx vss_ hv_io fec rxd[3] fec rx_er fec rxd[1] fec tx_er fec tx_ clk can0 txd vdd_ hv_io vss_ hv_io b c vdd_ hv_io nexus mdo [15] vss_ hv_io fccu_ f[1] flexray cb_rx etimer0 etc[0] etimer0 etc[1] etimer0 etc[2] etimer0 etc[3] jcomp fec crs fec txd[0] fec col can0 rxd vss_ hv_pdi pdi data [5] pdi clock c d nexus mdo [2] nexus mdo [3] can1 rxd dspi0 sout reserv ed etimer0 etc[5] etimer0 etc[4] vdd_ hv_fla vss_ hv_fla fec txd[2] fec txd[1] fec rx_dv fec mdc vdd_ hv_pdi vss_ hv_io pdi data [0] pdi data [1] d e nexus mdo [0] nexus mdo [1] flexray ca_rx nmi pdi line_v pdi data [2] pdi data [3] pdi data [4] e f nexus mdo[6] nexus mdo [11] dspi1 sout dspi1 sin vdd_ lv _ cor vdd_ lv _ cor vdd_ lv _ cor vdd_ lv _ cor vdd_ lv _ cor vdd_ lv _ cor vdd_ lv _ cor mc_cgl clk_out pdi data [6] pdi data [7] pdi data [8] f g nexus mdo [4] vdd_ hv_io dspi0 sck dspi1 sck vdd_ lv _ cor vss_ lv _ cor vss_ lv _ cor vss_ lv _ cor vss_ lv _ cor vss_ lv _ cor vdd_ lv _ cor pdi data [9] pdi data [10] pdi data [11] pdi frame_ v g h nexus mdo [10] vss_ hv_io dspi0 cs0 dspi1 cs0 vdd_ lv _ cor vss_ lv _ cor vss_ lv _ cor vss_ lv _ cor vss_ lv _ cor vss_ lv _ cor vdd_ lv _ cor pdi data [12] pdi data [13] vdd_ hv_ pdi flexpwm 0 x[0] h j nexus mcko nexus mdo[8] dspi2 cs0 dspi2 cs2 vdd_ lv _ cor vss_ lv _ cor vss_ lv _ cor vss_ lv _ cor vss_ lv _ cor vss_ lv _ cor vdd_ lv _ cor pdi data [14] pdi data [15] vss_ hv_ pdi flexpwm 0 x[1] j k nexus mseo_ b[0] nexus mseo_ b[1] nexus rdy_b dspi0 sin vdd_ lv _ cor vss_ lv _ cor vss_ lv _ cor vss_ lv _ cor vss_ lv _ cor vss_ lv _ cor vdd_ lv _ cor flexpwm 0 x[2] flexpwm 0 x[3] flexpwm 0 a[1] flexpwm 0 b[0] k l nexus evto_b nexus evti_b dspi2 sck nexus mdo [13] vdd_ lv _ cor vss_ lv _ cor vss_ lv _ cor vss_ lv _ cor vss_ lv _ cor vss_ lv _ cor vdd_ lv _ cor vdd_hv _dram_ vref tck flexpwm 0 b[1] tdo l m vdd_ hv_ osc vdd_ hv_io dspi1 cs2 nexus mdo [12] vdd_ lv _ cor vdd_ lv _ cor vdd_ lv _ cor vdd_ lv _ cor vdd_ lv _ cor vdd_ lv _ cor vdd_ lv _ cor flexpwm 0 b[2] tdi tms flexpwm 1 a[1] m n xtalin vss_ hv_io dspi0 cs3 vss_ lv _ p l l flexpwm 0 b[3] flexpwm 0 a[2] flexpwm 1 a[0] flexpwm 1 b[0] n p vss_ hv_ osc reset dspi0 cs2 vdd_ lv _ p l l etimer1 etc[1] etimer1 etc[2] adc0 an[0] etimer1 etc[3] vss_ hv_io vdd_ hv_io adc0_ adc1 an[14] etimer1 etc[4] etimer1 etc[5] vdd_ hv_io flexpwm 0 a[3] flexpwm 0 a[0] flexpwm 1 b[1] p r xtal out fccu_ f[0] vss_hv _io dspi1 cs3 adc2 an[0] adc2 an[3] vdd_ hv_ adr_13 adc2_ adc3 an[14] vdd_ hv_ adr_02 adc0 an[2] adc0_ adc1 an[13] adc1 an[1] vreg_c trl lin0 txd vss_ hv_io flexpwm 1 a[2] flexpwm 1 b[2] r t vss_ hv_io vdd_ hv_io dspi2 sout adc3 an[0] adc3 an[3] adc2 an[2] vss_ hv_ adr_13 adc2_ adc3 an[13] vss_ hv_ adr_02 adc0 an[1] adc0_ adc1 an[12] adc1 an[0] adc1 an[2] lin0 rxd etimer1 etc[0] vdd_ hv_io vss_ hv_io t u vss_ hv_io vss_ hv_io dspi2 sin adc3 an[1] adc3 an[2] adc2 an[1] adc2_ adc3 an[11] adc2_ adc3 an[12] vdd_ hv_ adv vss_ hv_ adv adc0_ adc1 an[11] vreg_ int_en able reset_ sup vdd_hv _pmu vss_ hv_ pmu vss_ hv_io vss_ hv_io u 1234567891011121314151617
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 20 figure 3. mpc5675k 473 mapbga pinout (northwest, viewed from above) figure 4. mpc5675k 473 mapbga pinout (southwest, viewed from above) 123456789101112 a vss_ hv_io vss_ hv_io vdd_ hv_io nexus mdo[5] nexus mdo[7] nexus mdo[9] flexray cb_tx flexray ca_tr_en fec rx_dv fec mdio fec tx_clk fec tx_en b vss_ hv_io vss_ hv_io mc_cgl clk_out can1 txd nexus mdo[14] dspi2 cs1 flexray cb_tr_en flexray ca_tx fec rxd[3] fec rx_er fec txd[0] fec rxd[0] c vdd_ hv_io nexus mdo[15] vss_ hv_io fccu_ f[1] flexray cb_rx etimer0 etc[4] etimer0 etc[1] etimer0 etc[2] etimer0 etc[3] fec txd[2] fec txd[1] fec crs d nexus mdo[1] nexus mdo[3] can1 rxd dspi0 sout reserved etimer0 etc[5] etimer0 etc[0] vdd_ hv_io vss_ hv_io jcomp vss_ hv_io vss_ hv_fla e nexus mdo[0] nexus mdo[2] flexray ca_rx nmi f nexus mdo[10] nexus mdo[11] nexus mdo[6] nexus mdo[4] vdd_ lv _ c o r vdd_ lv _ c o r vdd_ lv _ c o r vdd_ lv_c o r vdd_ lv_c o r vdd_ lv_ c or vdd_ lv_ c or g nexus mcko vdd_ hv_io nexus mdo[8] nexus mseo_b[1] vdd_ lv _ c o r vss_ lv _ c o r vss_ lv _ c o r vss_ lv_c o r vss_ lv_c o r vss_ lv_ c or vss_ lv_ c or h nexus evto_b vss_ hv_io nexus mseo_b[0] nexus evti_b vdd_ lv _ c o r vss_ lv _ c o r vss_ lv _ c o r vss_ lv_c o r vss_ lv_c o r vss_ lv_ c or vss_ lv_ c or j nexus rdy_b nexus mdo[13] nexus mdo[12] dspi1 sin vdd_ lv _ c o r vss_ lv _ c o r vss_ lv _ c o r vss_ lv_c o r vss_ lv_c o r vss_ lv_ c or vss_ lv_ c or k dspi0 sck dspi1 cs0 dspi1 sck dspi1 sout vdd_ lv _ c o r vss_ lv _ c o r vss_ lv _ c o r vss_ lv_c o r vss_ lv_c o r vss_ lv_ c or vss_ lv_ c or l dspi0 cs0 dspi2 cs2 dspi2 cs0 vss_ hv_io vdd_ lv _ c o r vss_ lv _ c o r vss_ lv _ c o r vss_ lv_c o r vss_ lv_c o r vss_ lv_ c or vss_ lv_ c or m flexpwm0 x[0] vdd_ hv_io dspi0 sin vdd_ hv_io vdd_ lv _ c o r vss_ lv _ c o r vss_ lv _ c o r vss_ lv_c o r vss_ lv_c o r vss_ lv_ c or vss_ lv_ c or n flexpwm0 a[0] vss_ hv_io flexpwm0 x[1] flexpwm0 b[2] vdd_ lv _ c o r vss_ lv _ c o r vss_ lv _ c o r vss_ lv_ c or vss_ lv_ c or vss_ lv_ c or vss_ lv_ c or p flexpwm0 b[0] flexpwm0 b[1] flexpwm0 a[2] flexpwm0 a[3] vdd_ lv _ c o r vss_ lv _ c o r vss_ lv _ c o r vss_ lv_ c or vss_ lv_ c or vss_ lv_ c or vss_ lv_ c or r flexpwm0 x[2] flexpwm0 x[3] flexpwm0 a[1] vss_ hv_io vdd_ lv _ c o r vss_ lv _ c o r vss_ lv _ c o r vss_ lv_ c or vss_ lv_ c or vss_ lv_ c or vss_ lv_ c or t flexpwm0 b[3] flexpwm1 a[0] flexpwm1 a[1] vdd_ hv_io vdd_ lv _ c o r vss_ lv _ c o r vss_ lv _ c o r vss_ lv_ c or vss_ lv_ c or vss_ lv_ c or vss_ lv_ c or u flexpwm1 b[0] flexpwm1 b[1] flexpwm1 a[2] dspi2 sck vdd_ lv _ c o r vss_ lv _ c o r vss_ lv _ c o r vss_ lv_ c or vss_ lv_ c or vss_ lv_ c or vss_ lv_ c or v vdd_ hv_osc vdd_ hv_io flexpwm1 b[2] dspi1 cs2 vdd_ lv _ c o r vdd_ lv _ c o r vdd_ lv _ c o r vdd_ lv_ c or vdd_ lv_ c or vdd_ lv_ c or vdd_ lv_ c or w xtalin vss_ hv_io dspi0 cs3 vss_ lv_pll y vss_ hv_osc reset dspi0 cs2 vdd_ lv_pll flexpwm1 x[0] adc3 an[0] adc2_adc3 an[11] adc2_adc3 an[14] etimer1 etc[1] etimer1 etc[2] etimer1 etc[3] vss_ hv_io aa xtalout fccu_ f[0] vss_ hv_io dspi1 cs3 flexpwm1 x[1] adc3 an[1] adc2_adc3 an[12] adc2 an[0] vdd_ hv_adv vss_ hv_adv adc0 an[2] adc0 an[5] ab vss_ hv_io vdd_ hv_io dspi2 sout flexpwm1 x[2] flexpwm1 x[3] adc3 an[2] adc2_adc3 an[13] adc2 an[1] adc2 an[2] adc0 an[0] adc0 an[4] adc0 an[6] ac vss_ hv_io vss_ hv_io dspi2 sin flexpwm1 a[3] flexpwm1 b[3] adc3 an[3] vdd_hv_ adr_23 vss_hv_ adr_23 adc2 an[3] adc0 an[1] adc0 an[3] vdd_ hv_adr_0 123456789101112
package pinouts and signal descriptions mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 21 figure 5. mpc5675k 473 mapbga pinout (northeast, viewed from above) figure 6. mpc5675k 473 mapbga pinout (southeast, viewed from above) 13 14 15 16 17 18 19 20 21 22 23 fec txd[3] vdd_ hv_io pdi data[3] pdi data[1] pdi clock pdi data[7] pdi data[10] pdi data[13] pdi data[15] vss_ hv_io vss_ hv_io a fec tx_er vss_ hv_io pdi data[6] pdi data[4] pdi data[0] pdi line_v pdi data[9] pdi data[14] can0 txd vdd_ hv_io vss_ hv_io b fec rx_clk fec rxd[1] fec col pdi data[5] pdi data[2] pdi data[8] pdi data[12] can0 rxd vss_ hv_pdi siul gpio[197] dramc cas c vdd_ hv_fla fec rxd[2] fec mdc vdd_ hv_pdi vss_ hv_pdi pdi data[11] pdi frame_v vdd_ hv_pdi dramc ba[1] siul gpio[195] dramc ba[0] d mc_cgl clk_out siul gpio[149] dramc cs0 dramc ba[2] e vdd_ lv _ c o r vdd_ lv _ c o r vdd_ lv_ c or vdd_ lv_ c or vdd_ lv _ c o r vdd_ lv _ c o r dramc ras siul gpio[194] siul gpio[148] dramc d[5] f vss_ lv _ c o r vss_ lv _ c o r vss_ lv_ c or vss_ lv_ c or vss_ lv _ c o r vdd_ lv _ c o r siul gpio[196] dramc dqs[0] dramc dm[0] dramc d[7] g vss_ lv _ c o r vss_ lv _ c o r vss_ lv_ c or vss_ lv_ c or vss_ lv _ c o r vdd_ lv _ c o r dramc d[2] vdd_hv_ dram_vtt vdd_hv_ dram vss_hv_ dram h vss_ lv _ c o r vss_ lv _ c o r vss_ lv_ c or vss_ lv_ c or vss_ lv _ c o r vdd_ lv _ c o r dramc d[0] dramc d[1] dramc d[3] dramc d[6] j vss_ lv _ c o r vss_ lv _ c o r vss_ lv_ c or vss_ lv_ c or vss_ lv _ c o r vdd_ lv _ c o r vss_ hv_io dramc d[4] dramc d[8] dramc d[9] k vss_ lv _ c o r vss_ lv _ c o r vss_ lv_ c or vss_ lv_ c or vss_ lv _ c o r vdd_ lv _ c o r vdd_ hv_io vdd_hv_ dram_vtt vss_hv_ dram vdd_hv_ dram l vss_ lv _ c o r vss_ lv _ c o r vss_ lv_ c or vss_ lv_ c or vss_ lv _ c o r vdd_ lv _ c o r dramc odt dramc web dramc d[11] dramc d[10] m vss_ lv _ c o r vss_ lv _ c o r vss_ lv_ c or vss_ lv_ c or vss_ lv _ c o r vdd_ lv _ c o r dramc dqs[1] dramc dm[1] dramc d[13] dramc d[12] n vss_ lv _ c o r vss_ lv _ c o r vss_ lv_ c or vss_ lv_ c or vss_ lv _ c o r vdd_ lv _ c o r dramc d[14] dramc d[15] vss_hv_ dram vdd_hv_ dram p vss_ lv _ c o r vss_ lv _ c o r vss_ lv_ c or vss_ lv_ c or vss_ lv _ c o r vdd_ lv _ c o r vdd_hv_ dram_vref dramc add[3] dramc cke dramc clkb r vss_ lv _ c o r vss_ lv _ c o r vss_ lv_ c or vss_ lv_ c or vss_ lv _ c o r vdd_ lv _ c o r dramc add[8] dramc add[9] dramc add[1] dramc clk t vss_ lv _ c o r vss_ lv _ c o r vss_ lv_ c or vss_ lv_ c or vss_ lv _ c o r vdd_ lv _ c o r dramc add[6] dramc add[12] vdd_hv_ dram dramc add[0] u vdd_ lv _ c o r vdd_ lv _ c o r vdd_ lv_ c or vdd_ lv_ c or vdd_ lv _ c o r vdd_ lv _ c o r lin0 txd dramc add[13] vss_hv_ dram dramc add[2] v lin0 rxd dramc add[14] dramc add[7] dramc add[4] w vdd_ hv_io adc0_adc1 an[11] etimer1 etc[5] etimer1 etc[4] adc1 an[8] adc1 an[6] tck vdd_hv_io dramc add[15] dramc add[11] dramc add[5] y adc0 an[8] adc0_adc1 an[12] adc1 an[0] adc1 an[2] adc1 an[5] adc1 an[7] tdi etimer1 etc[0] vss_hv_io lin1 txd dramc add[10] aa adc0 an[7] adc0_adc1 an[13] adc1 an[1] adc1 an[3] adc1 an[4] tdo tms reserved lin1 rxd vdd_ hv_io vss_ hv_io ab vss_ hv_adr_0 adc0_adc1 an[14] vdd_ hv_adr_1 vss_ hv_adr_1 vdd_ hv_pmu vreg_ctrl vss_ hv_pmu reset_ sup vreg_int_ enable vss_ hv_io vss_ hv_io ac 13 14 15 16 17 18 19 20 21 22 23
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 22 2.2 pin descriptions the following sections provide signa l descriptions and related inform ation about the f unctionality and configuration for this device. 2.2.1 pad types table 2 lists the pad types used on the mpc5675k. table2. pad types pad type description gp slow slow buffer with cmos sc hmitt trigger and pullup/pulldown. gp slow/fast programmable slow/fast buffer with cmos schmitt trigger, pullup/pulldown. gp slow/medium programmable slow/medium buffer with cmos schmitt trigger, pullup/pulldown. programmable slow/medium buffer with cmos schmitt trigger, pullup/pulldown and injection proof analog switch. gp slow/symmetric programmable slow/symmetric buffer with cmos schmitt trigger, pullup/pulldown. pdi medium medium slew-rate output with four sele ctable slew rates. contains an input buffer and weak pullup/pulldown. pdi fast fast slew-rate output with four selectable slew rates. contains an input buffer and weak pullup/pulldown. dram acc bidirectional ddr pad. can be conf igured to support lpddr half strength, lpddr full strength, ddr1, ddr2 half st rength, ddr2 full st rength, and sdr. dram clk differential clock driver dram dq bidirectional ddr pad with integrated odt. can be configured to support lpddr half strength, lpddr full strength, ddr1, ddr2 half strength, ddr2 full strength, and sdr. dram odt ctl enable on die termination control analog cmos schmitt trigger cell with injection proof analog switch. analog shared cmos schmitt trigger cell with two injection-proof analog switches.
package pinouts and signal descriptions mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 23 2.2.2 power supply and reference voltage pins table 3 shows the supply pins for the mp c5675k in the 257 mapbga package. table 5 shows the supply pins for the mpc5675k in the 473 mapbga package. table 4 and table 6 show the pins not populated on the mpc5675k 257 mapbga and 473 mapbga packages, respectively. table 3. 257 mapbga supply pins ball number ball name pad type ball number ball name pad type v dd a3 vdd_hv_io vdd_hv f9 vdd_lv_cor vdd_lv a9 vdd_hv_io vdd_hv f10 vdd_lv_cor vdd_lv b16 vdd_hv_io vdd_hv f11 vdd_lv_cor vdd_lv c1 vdd_hv_io vdd_hv f12 vdd_lv_cor vdd_lv g2 vdd_hv_io vdd_hv g6 vdd_lv_cor vdd_lv m2 vdd_hv_io vdd_hv g12 vdd_lv_cor vdd_lv p10 vdd_hv_io vdd_hv h6 vdd_lv_cor vdd_lv p14 vdd_hv_io vdd_hv h12 vdd_lv_cor vdd_lv t2 vdd_hv_io vdd_hv j6 vdd_lv_cor vdd_lv t16 vdd_hv_io vdd_hv j12 vdd_lv_cor vdd_lv l14 vdd_hv_dram_vref vdd_hv k6 vdd_lv_cor vdd_lv d8 vdd_hv_fla vdd_hv k12 vdd_lv_cor vdd_lv m1 vdd_hv_osc vdd_hv l6 vdd_lv_cor vdd_lv d14 vdd_hv_pdi vdd_hv l12 vdd_lv_cor vdd_lv h16 vdd_hv_pdi vdd_hv m6 vdd_lv_cor vdd_lv u14 vdd_hv_pmu vdd_hv m7 vdd_lv_cor vdd_lv r7 vdd_hv_adr_13 vdd_hv_a m8 vdd_lv_cor vdd_lv r9 vdd_hv_adr_02 vdd_hv_a m9 vdd_lv_cor vdd_lv u9 vdd_hv_adv vdd_hv_a m10 vdd_lv_cor vdd_lv f6 vdd_lv_cor vdd_lv m11 vdd_lv_cor vdd_lv f7 vdd_lv_cor vdd_lv m12 vdd_lv_cor vdd_lv f8 vdd_lv_cor vdd_lv p4 vdd_lv_pll vdd_lv v ss a1 vss_hv_io vss_hv g7 vss_lv_cor vss_lv a2 vss_hv_io vss_hv g8 vss_lv_cor vss_lv a16 vss_hv_io vss_hv g9 vss_lv_cor vss_lv a17 vss_hv_io vss_hv g10 vss_lv_cor vss_lv
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 24 b1 vss_hv_io vss_hv g11 vss_lv_cor vss_lv b2 vss_hv_io vss_hv h7 vss_lv_cor vss_lv b9 vss_hv_io vss_hv h8 vss_lv_cor vss_lv b17 vss_hv_io vss_hv h9 vss_lv_cor vss_lv c3 vss_hv_io vss_hv h10 vss_lv_cor vss_lv d15 vss_hv_io vss_hv h11 vss_lv_cor vss_lv h2 vss_hv_io vss_hv j7 vss_lv_cor vss_lv n2 vss_hv_io vss_hv j8 vss_lv_cor vss_lv p9 vss_hv_io vss_hv j9 vss_lv_cor vss_lv r3 vss_hv_io vss_hv j10 vss_lv_cor vss_lv r15 vss_hv_io vss_hv j11 vss_lv_cor vss_lv t1 vss_hv_io vss_hv k7 vss_lv_cor vss_lv t17 vss_hv_io vss_hv k8 vss_lv_cor vss_lv u1 vss_hv_io vss_hv k9 vss_lv_cor vss_lv u2 vss_hv_io vss_hv k10 vss_lv_cor vss_lv u16 vss_hv_io vss_hv k11 vss_lv_cor vss_lv u17 vss_hv_io vss_hv l7 vss_lv_cor vss_lv d9 vss_hv_fla vss_hv l8 vss_lv_cor vss_lv p1 vss_hv_osc vss_hv l9 vss_lv_cor vss_lv c15 vss_hv_pdi vss_hv l10 vss_lv_cor vss_lv j16 vss_hv_pdi vss_hv l11 vss_lv_cor vss_lv t9 vss_hv_adr_02 vss_hv_a n4 vss_lv_pll vss_lv t7 vss_hv_adr_13 vss_hv_a u15 vss_hv_pmu vss_lv u10 vss_hv_adv vss_hv_a table4. 257mapbga balls not populated on package e5 e6 e7 e8 e9 e10 e11 e12 e13 f5 f13 g5 g13 h5 h13 j5 j13 k5 k13 l5 l13 m5 m13 n5 n6 n7 n8 n9 n10 n11 n12 n13 table 3. 257 mapbga supply pins (continued) ball number ball name pad type ball number ball name pad type
package pinouts and signal descriptions mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 25 table 5. 473 mapbga supply pins ball number ball name pad type ball number ball name pad type v dd a3 vdd_hv_io vdd_hv f15 vdd_lv_cor vdd_lv a14 vdd_hv_io vdd_hv f16 vdd_lv_cor vdd_lv b22 vdd_hv_io vdd_hv f17 vdd_lv_cor vdd_lv c1 vdd_hv_io vdd_hv f18 vdd_lv_cor vdd_lv d8 vdd_hv_io vdd_hv g6 vdd_lv_cor vdd_lv g2 vdd_hv_io vdd_hv g18 vdd_lv_cor vdd_lv l20 vdd_hv_io vdd_hv h6 vdd_lv_cor vdd_lv m2 vdd_hv_io vdd_hv h18 vdd_lv_cor vdd_lv m4 vdd_hv_io vdd_hv j6 vdd_lv_cor vdd_lv t4 vdd_hv_io vdd_hv j18 vdd_lv_cor vdd_lv v2 vdd_hv_io vdd_hv k6 vdd_lv_cor vdd_lv y13 vdd_hv_io vdd_hv k18 vdd_lv_cor vdd_lv y20 vdd_hv_io vdd_hv l6 vdd_lv_cor vdd_lv ab2 vdd_hv_io vdd_hv l18 vdd_lv_cor vdd_lv ab22 vdd_hv_io vdd_hv m6 vdd_lv_cor vdd_lv ac12 vdd_hv_adr_0 vdd_hv_a m18 vdd_lv_cor vdd_lv ac15 vdd_hv_adr_1 vdd_hv_a n6 vdd_lv_cor vdd_lv ac7 vdd_hv_adr_23 vdd_hv_a n18 vdd_lv_cor vdd_lv aa9 vdd_hv_adv vdd_hv_a p6 vdd_lv_cor vdd_lv h22 vdd_hv_dram vdd_hv p18 vdd_lv_cor vdd_lv l23 vdd_hv_dram vdd_hv r6 vdd_lv_cor vdd_lv p23 vdd_hv_dram vdd_hv r18 vdd_lv_cor vdd_lv u22 vdd_hv_dram vdd_hv t6 vdd_lv_cor vdd_lv r20 vdd_hv_dram_vref vdd_hv t18 vdd_lv_cor vdd_lv h21 vdd_hv_dram_vtt vdd_hv u6 vdd_lv_cor vdd_lv l21 vdd_hv_dram_vtt vdd_hv u18 vdd_lv_cor vdd_lv d13 vdd_hv_fla vdd_hv v6 vdd_lv_cor vdd_lv v1 vdd_hv_osc vdd_hv v7 vdd_lv_cor vdd_lv d16 vdd_hv_pdi vdd_hv v8 vdd_lv_cor vdd_lv d20 vdd_hv_pdi vdd_hv v9 vdd_lv_cor vdd_lv ac17 vdd_hv_pmu vdd_hv v10 vdd_lv_cor vdd_lv f6 vdd_lv_cor vdd_lv v11 vdd_lv_cor vdd_lv f7 vdd_lv_cor vdd_lv v12 vdd_lv_cor vdd_lv
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 26 f8 vdd_lv_cor vdd_lv v13 vdd_lv_cor vdd_lv f9 vdd_lv_cor vdd_lv v14 vdd_lv_cor vdd_lv f10 vdd_lv_cor vdd_lv v15 vdd_lv_cor vdd_lv f11 vdd_lv_cor vdd_lv v16 vdd_lv_cor vdd_lv f12 vdd_lv_cor vdd_lv v17 vdd_lv_cor vdd_lv f13 vdd_lv_cor vdd_lv v18 vdd_lv_cor vdd_lv f14 vdd_lv_cor vdd_lv y4 vdd_lv_pll vdd_lv v ss a2 vss_hv_io vss_hv l7 vss_lv_cor vss_lv a22 vss_hv_io vss_hv l8 vss_lv_cor vss_lv a23 vss_hv_io vss_hv l9 vss_lv_cor vss_lv b1 vss_hv_io vss_hv l10 vss_lv_cor vss_lv b2 vss_hv_io vss_hv l11 vss_lv_cor vss_lv b14 vss_hv_io vss_hv l12 vss_lv_cor vss_lv b23 vss_hv_io vss_hv l13 vss_lv_cor vss_lv c3 vss_hv_io vss_hv l14 vss_lv_cor vss_lv d9 vss_hv_io vss_hv l15 vss_lv_cor vss_lv d11 vss_hv_io vss_hv l16 vss_lv_cor vss_lv h2 vss_hv_io vss_hv l17 vss_lv_cor vss_lv k20 vss_hv_io vss_hv m7 vss_lv_cor vss_lv l4 vss_hv_io vss_hv m8 vss_lv_cor vss_lv n2 vss_hv_io vss_hv m9 vss_lv_cor vss_lv a1 vss_hv_io vss_hv m10 vss_lv_cor vss_lv r4 vss_hv_io vss_hv m11 vss_lv_cor vss_lv w2 vss_hv_io vss_hv m12 vss_lv_cor vss_lv y12 vss_hv_io vss_hv m13 vss_lv_cor vss_lv aa3 vss_hv_io vss_hv m14 vss_lv_cor vss_lv aa21 vss_hv_io vss_hv m15 vss_lv_cor vss_lv ab1 vss_hv_io vss_hv m16 vss_lv_cor vss_lv ab23 vss_hv_io vss_hv m17 vss_lv_cor vss_lv ac1 vss_hv_io vss_hv n7 vss_lv_cor vss_lv ac2 vss_hv_io vss_hv n8 vss_lv_cor vss_lv ac22 vss_hv_io vss_hv n9 vss_lv_cor vss_lv ac23 vss_hv_io vss_hv n10 vss_lv_cor vss_lv table 5. 473 mapbga supply pins (continued) ball number ball name pad type ball number ball name pad type
package pinouts and signal descriptions mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 27 ac13 vss_hv_adr_0 vss_hv_a n11 vss_lv_cor vss_lv ac16 vss_hv_adr_1 vss_hv_a n12 vss_lv_cor vss_lv ac8 vss_hv_adr_23 vss_hv_a n13 vss_lv_cor vss_lv aa10 vss_hv_adv vss_hv_a n14 vss_lv_cor vss_lv h23 vss_hv_dram vss_hv n15 vss_lv_cor vss_lv l22 vss_hv_dram vss_hv n16 vss_lv_cor vss_lv p22 vss_hv_dram vss_hv n17 vss_lv_cor vss_lv v22 vss_hv_dram vss_hv p7 vss_lv_cor vss_lv d12 vss_hv_fla vss_hv p8 vss_lv_cor vss_lv y1 vss_hv_osc vss_hv p9 vss_lv_cor vss_lv c21 vss_hv_pdi vss_hv p10 vss_lv_cor vss_lv d17 vss_hv_pdi vss_hv p11 vss_lv_cor vss_lv g7 vss_lv_cor vss_lv p12 vss_lv_cor vss_lv g8 vss_lv_cor vss_lv p13 vss_lv_cor vss_lv g9 vss_lv_cor vss_lv p14 vss_lv_cor vss_lv g10 vss_lv_cor vss_lv p15 vss_lv_cor vss_lv g11 vss_lv_cor vss_lv p16 vss_lv_cor vss_lv g12 vss_lv_cor vss_lv p17 vss_lv_cor vss_lv g13 vss_lv_cor vss_lv r7 vss_lv_cor vss_lv g14 vss_lv_cor vss_lv r8 vss_lv_cor vss_lv g15 vss_lv_cor vss_lv r9 vss_lv_cor vss_lv g16 vss_lv_cor vss_lv r10 vss_lv_cor vss_lv g17 vss_lv_cor vss_lv r11 vss_lv_cor vss_lv h7 vss_lv_cor vss_lv r12 vss_lv_cor vss_lv h8 vss_lv_cor vss_lv r13 vss_lv_cor vss_lv h9 vss_lv_cor vss_lv r14 vss_lv_cor vss_lv h10 vss_lv_cor vss_lv r15 vss_lv_cor vss_lv h11 vss_lv_cor vss_lv r16 vss_lv_cor vss_lv h12 vss_lv_cor vss_lv r17 vss_lv_cor vss_lv h13 vss_lv_cor vss_lv t7 vss_lv_cor vss_lv h14 vss_lv_cor vss_lv t8 vss_lv_cor vss_lv h15 vss_lv_cor vss_lv t9 vss_lv_cor vss_lv h16 vss_lv_cor vss_lv t10 vss_lv_cor vss_lv h17 vss_lv_cor vss_lv t11 vss_lv_cor vss_lv table 5. 473 mapbga supply pins (continued) ball number ball name pad type ball number ball name pad type
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 28 j7 vss_lv_cor vss_lv t12 vss_lv_cor vss_lv j8 vss_lv_cor vss_lv t13 vss_lv_cor vss_lv j9 vss_lv_cor vss_lv t14 vss_lv_cor vss_lv j10 vss_lv_cor vss_lv t15 vss_lv_cor vss_lv j11 vss_lv_cor vss_lv t16 vss_lv_cor vss_lv j12 vss_lv_cor vss_lv t17 vss_lv_cor vss_lv j13 vss_lv_cor vss_lv u7 vss_lv_cor vss_lv j14 vss_lv_cor vss_lv u8 vss_lv_cor vss_lv j15 vss_lv_cor vss_lv u9 vss_lv_cor vss_lv j16 vss_lv_cor vss_lv u10 vss_lv_cor vss_lv j17 vss_lv_cor vss_lv u11 vss_lv_cor vss_lv k7 vss_lv_cor vss_lv u12 vss_lv_cor vss_lv k8 vss_lv_cor vss_lv u13 vss_lv_cor vss_lv k9 vss_lv_cor vss_lv u14 vss_lv_cor vss_lv k10 vss_lv_cor vss_lv u15 vss_lv_cor vss_lv k11 vss_lv_cor vss_lv u16 vss_lv_cor vss_lv k12 vss_lv_cor vss_lv u17 vss_lv_cor vss_lv k13 vss_lv_cor vss_lv w4 vss_lv_pll vss_lv k14 vss_lv_cor vss_lv ac19 vss_hv_pmu vss_lv k15 vss_lv_cor vss_lv d5 reserved vss_hv k16 vss_lv_cor vss_lv ab20 reserved vss_hv k17 vss_lv_cor vss_lv table6. 473mapbga balls not populated on package e5 e6 e7 e8 e9 e10 e11 e12 e13 e14 e15 e16 e17 e18 e19 f5 f19 g5 g19 h5 h19 j5 j19 k5 k19 l5 l19 m5 m19 n5 n19 p5 p19 r5 r19 t5 t19 u5 u19 v5 v19w5w6w7w8w9w10w11 w12w13w14w15w16w17w18w19 table 5. 473 mapbga supply pins (continued) ball number ball name pad type ball number ball name pad type
package pinouts and signal descriptions mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 29 2.2.3 system pins table 7 shows the system pins for the mpc5675k in the 257 mapbga package. table 8 shows the system pins for the mpc5675k in the 473 mapbga package. table 7. 257 mapbga system pins ball number ball name weak pull during reset safe mode default condition pad type power domain c4 fccu_f[1] disabled not available gp slow/medium vdd_hv_io c10 jcomp pull down not available gp slow vdd_hv_io e1 nexus mdo[0] 1 notes: 1 do not connect pin directly to a power supply or ground. ? not available gp slow/fast vdd_hv_io e4 nmi pull up not available gp slow vdd_hv_io l15 tck pull up not available gp slow vdd_hv_io m16 tms pull up not available gp slow vdd_hv_io n1 xtalin ? not available analog feedthrough vdd_hv_io p2 reset pull down not available reset vdd_hv_io r1 xtalout ? not available analog feedthrough vdd_hv_io r2 fccu_f[0] disabled not available gp slow/medium vdd_hv_io r13 vreg_ctrl ?? analog feedthrough vdd_reg u12 vreg_int_enable ?? analog feedthrough vdd_hv_io u13 reset_sup pull down ? analog feedthrough vdd_hv_io table 8. 473 mapbga system pins ball number ball name weak pull during reset safe mode default condition pad type power domain c4 fccu_f[1] disabled not available gp slow/medium vdd_hv_io d10 jcomp pull down not available gp slow vdd_hv_io e1 nexus mdo[0] 1 notes: 1 do not connect pin directly to a power supply or ground. ? not available gp slow/fast vdd_hv_io e4 nmi pull up not available gp slow vdd_hv_io r23 dramc clkb ? ? dram clk vdd_hv_dram t23 dramc clk disabled ? dram clk vdd_hv_dram w1 xtalin ? not available analog feedthrough vdd_hv_io y2 reset pull down not available reset vdd_hv_io y19 tck pull up not available gp slow vdd_hv_io aa1 xtalout ? not available analog feedthrough vdd_hv_io aa2 fccu_f[0] disabled not available gp slow/medium vdd_hv_io ab19 tms pull up not available gp slow vdd_hv_io ac18 vreg_ctrl ? ? analog feedthrough vdd_reg ac20 reset_sup pull down ? analog feedthrough vdd_hv_io ac21 vreg_int_enable ? ? analog feedthrough vdd_hv_io
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 30 2.2.4 multiplexed pins table 9 shows the pin multiplexing for the mp c5675k in the 257 mapbga package. table 10 shows the pin multiplexing for the mpc5675k in the 473 mapbga package. table 9. 257 mapbga pin multiplexing ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain a4 gpio nexus mdo[5] 1 a0: siul_gpio[114] a1: _ a2: npc_wrapper_mdo[5] a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io a5 gpio nexus mdo[7] 1 a0: siul_gpio[112] a1: _ a2: npc_wrapper_mdo[7] a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io a6 gpio nexus mdo[9] 1 a0: siul_gpio[110] a1: _ a2: npc_wrapper_mdo[9] a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io a7 gpio flexray cb_tx a0: siul_gpio[51] a1: flexray_cb_tx a2: _ a3: _ i: _ i: _ i: _ ? disabled gp slow/ symmetric vdd_hv_io a8 gpio flexray ca_tr_en a0: siul_gpio[47] a1: flexray_ca_tr_en a2: _ a3: _ i: ctu0_ext_in i: flexpwm0_ext_sync i: _ ? disabled gp slow/ symmetric vdd_hv_io a10 gpio fec rxd[2] a0: siul_gpio[213] a1: _ a2: _ a3: dspi2_sout i: fec_rxd[2] i: _ i: siul_eirq[21] ? disabled gp slow/ medium vdd_hv_io a11 gpio fec rx_clk a0: siul_gpio[209] a1: flexray_dbg2 a2: etimer2_etc[2] a3: dspi0_cs6 i: fec_rx_clk i: _ i: siul_eirq[25] ? disabled gp slow/ medium vdd_hv_io
package pinouts and signal descriptions mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 31 a12 gpio fec rxd[0] a0: siul_gpio[211] a1: i2c1_clock a2: _ a3: _ i: fec_rxd[0] i: _ i: siul_eirq[27] ? disabled gp slow/ medium vdd_hv_io a13 gpio fec mdio a0: siul_gpio[198] a1: fec_mdio a2: _ a3: dspi2_cs0 i: _ i: _ i: siul_eirq[28] ? disabled gp slow/ medium vdd_hv_io a14 gpio fec tx_en a0: siul_gpio[200] a1: fec_tx_en a2: _ a3: lin0_txd i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io a15 gpio fec txd[3] a0: siul_gpio[204] a1: fec_txd[3] a2: _ a3: dspi2_cs2 i: flexpwm1_fault[2] i: _ i: siul_eirq[29] ? disabled gp slow/ medium vdd_hv_io b3 gpio mc_cgl clk_out a0: siul_gpio[22] a1: mc_cgl_clk_out a2: etimer2_etc[5] a3: _ i: _ i: _ i: siul_eirq[18] ? disabled gp slow/ fast vdd_hv_io b4 gpio can1 txd a0: siul_gpio[14] a1: can1_txd a2: _ a3: _ i: _ i: _ i: siul_eirq[13] ? disabled gp slow/ medium vdd_hv_io b5 gpio nexus mdo[14] 1 a0: siul_gpio[219] a1: _ a2: npc_wrapper_mdo[14] a3: can3_txd i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io b6 gpio dspi2 cs1 a0: siul_gpio[9] a1: dspi2_cs1 a2: _ a3: _ i: flexpwm0_fault[0] i: lin3_rxd i: can2_rxd ? disabled gp slow/ medium vdd_hv_io b7 gpio flexray cb_tr_en a0: siul_gpio[52] a1: flexray_cb_tr_en a2: _ a3: _ i: _ i: _ i: _ ? disabled gp slow/ symmetric vdd_hv_io table 9. 257 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 32 b8 gpio flexray ca_tx a0: siul_gpio[48] a1: flexray_ca_tx a2: _ a3: _ i: ctu1_ext_in i: _ i: _ ? disabled gp slow/ symmetric vdd_hv_io b10 gpio fec rxd[3] a0: siul_gpio[214] a1: i2c1_data a2: _ a3: _ i: fec_rxd[3] i: _ i: _ ? disabled gp slow/ medium vdd_hv_io b11 gpio fec rx_er a0: siul_gpio[215] a1: _ a2: _ a3: dspi0_cs1 i: fec_rx_er i: _ i: _ ? disabled gp slow/ medium vdd_hv_io b12 gpio fec rxd[1] a0: siul_gpio[212] a1: dspi1_cs1 a2: etimer2_etc[5] a3: _ i: fec_rxd[1] i: _ i: _ ? disabled gp slow/ medium vdd_hv_io b13 gpio fec tx_er a0: siul_gpio[205] a1: fec_tx_er a2: dspi2_cs3 a3: _ i: flexpwm1_fault[3] i: lin0_rxd i: _ ? disabled gp slow/ medium vdd_hv_io b14 gpio fec tx_clk a0: siul_gpio[207] a1: flexray_dbg0 a2: etimer2_etc[4] a3: dspi0_cs4 i: fec_tx_clk i: _ i: _ ? disabled gp slow/ medium vdd_hv_io b15 gpio can0 txd a0: siul_gpio[16] a1: can0_txd a2: _ a3: sscm_debug[0] i: _ i: _ i: siul_eirq[15] ? disabled gp slow/ medium vdd_hv_io c2 gpio nexus mdo[15] 1 a0: siul_gpio[220] a1: _ a2: npc_wrapper_mdo[15] a3: _ i: can3_rxd i: can2_rxd i: _ ? disabled gp slow/ fast vdd_hv_io c5 gpio flexray cb_rx a0: siul_gpio[50] a1: _ a2: ctu1_ext_tgr a3: _ i: flexray_cb_rx i: _ i: _ ? disabled gp slow/ medium vdd_hv_io table 9. 257 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
package pinouts and signal descriptions mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 33 c6 gpio etimer0 etc[0] a0: siul_gpio[0] a1: etimer0_etc[0] a2: _ a3: _ i: dspi2_sin i: _ i: siul_eirq[0] ? disabled gp slow/ medium vdd_hv_io c7 gpio etimer0 etc[1] a0: siul_gpio[1] a1: etimer0_etc[1] a2: _ a3: _ i: _ i: _ i: siul_eirq[1] ? disabled gp slow/ medium vdd_hv_io c8 gpio etimer0 etc[2] a0: siul_gpio[2] a1: etimer0_etc[2] a2: _ a3: _ i: _ i: _ i: siul_eirq[2] ? disabled gp slow/ medium vdd_hv_io c9 gpio etimer0 etc[3] a0: siul_gpio[3] a1: etimer0_etc[3] a2: _ a3: _ i: _ i: mc_rgm_abs[2] i: siul_eirq[3] ? pull down gp slow/ medium vdd_hv_io c11 gpio fec crs a0: siul_gpio[208] a1: flexray_dbg1 a2: etimer2_etc[3] a3: dspi0_cs5 i: fec_crs i: _ i: _ ? disabled gp slow/ medium vdd_hv_io c12 gpio fec txd[0] a0: siul_gpio[201] a1: fec_txd[0] a2: etimer2_etc[1] a3: _ i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io c13 gpio fec col a0: siul_gpio[206] a1: fec_col a2: _ a3: lin1_txd i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io c14 gpio can0 rxd a0: siul_gpio[17] a1: _ a2: _ a3: sscm_debug[1] i: can0_rxd i: can1_rxd i: siul_eirq[16] ? disabled gp slow/ medium vdd_hv_io c16 gpio pdi data[5] a0: siul_gpio[136] a1: flexpwm2_a[0] a2: _ a3: etimer1_etc[0] i: pdi_data[5] i: _ i: _ ? disabled pdi medium vdd_hv_pdi table 9. 257 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 34 c17 gpio pdi clock a0: siul_gpio[128] a1: flexpwm2_b[1] a2: _ a3: etimer1_etc[3] i: pdi_clock i: _ i: _ ? disabled pdi medium vdd_hv_pdi d1 gpio nexus mdo[2] 1 a0: siul_gpio[85] a1: _ a2: npc_wrapper_mdo[2] a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io d2 gpio nexus mdo[3] 1 a0: siul_gpio[84] a1: _ a2: npc_wrapper_mdo[3] a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io d3 gpio can1 rxd a0: siul_gpio[15] a1: _ a2: _ a3: _ i: can1_rxd i: can0_rxd i: siul_eirq[14] ? disabled gp slow/ medium vdd_hv_io d4 gpio dspi0 sout a0: siul_gpio[38] a1: dspi0_sout a2: _ a3: sscm_debug[6] i: _ i: _ i: siul_eirq[24] ? disabled gp slow/ medium vdd_hv_io d6 gpio etimer0 etc[5] a0: siul_gpio[44] a1: etimer0_etc[5] a2: _ a3: _ i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io d7 gpio etimer0 etc[4] a0: siul_gpio[43] a1: etimer0_etc[4] a2: _ a3: _ i: _ i: mc_rgm_abs[0] i: _ ? pull down gp slow/ medium vdd_hv_io d10 gpio fec txd[2] a0: siul_gpio[203] a1: fec_txd[2] a2: _ a3: _ i: flexpwm1_fault[1] i: _ i: _ ? disabled gp slow/ medium vdd_hv_io d11 gpio fec txd[1] a0: siul_gpio[202] a1: fec_txd[1] a2: _ a3: dspi2_sck i: flexpwm1_fault[0] i: _ i: _ ? disabled gp slow/ medium vdd_hv_io table 9. 257 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
package pinouts and signal descriptions mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 35 d12 gpio fec rx_dv a0: siul_gpio[210] a1: flexray_dbg3 a2: etimer2_etc[0] a3: dspi0_cs7 i: fec_rx_dv i: _ i: _ ? disabled gp slow/ medium vdd_hv_io d13 gpio fec mdc a0: siul_gpio[199] a1: fec_mdc a2: _ a3: _ i: _ i: lin1_rxd i: _ ? disabled gp slow/ medium vdd_hv_io d16 gpio pdi data[0] a0: siul_gpio[131] a1: _ a2: lin3_txd a3: _ i: pdi_data[0] i: _ i: flexpwm2_fault[2] ? disabled pdi medium vdd_hv_pdi d17 gpio pdi data[1] a0: siul_gpio[132] a1: flexpwm2_b[3] a2: _ a3: _ i: pdi_data[1] i: _ i: _ ? disabled pdi medium vdd_hv_pdi e2 gpio nexus mdo[1] 1 a0: siul_gpio[86] a1: _ a2: npc_wrapper_mdo[1] a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io e3 gpio flexray ca_rx a0: siul_gpio[49] a1: _ a2: ctu0_ext_tgr a3: _ i: flexray_ca_rx i: _ i: _ ? disabled gp slow/ medium vdd_hv_io e14 gpio pdi line_v a0: siul_gpio[129] a1: _ a2: lin2_txd a3: _ i: pdi_line_v i: _ i: flexpwm2_fault[0] ? disabled pdi medium vdd_hv_pdi e15 gpio pdi data[2] a0: siul_gpio[133] a1: flexpwm2_a[1] a2: _ a3: etimer1_etc[2] i: pdi_data[2] i: _ i: _ ? disabled pdi medium vdd_hv_pdi e16 gpio pdi data[3] a0: siul_gpio[134] a1: flexpwm2_x[1] a2: _ a3: _ i: pdi_data[3] i: _ i: _ ? disabled pdi medium vdd_hv_pdi table 9. 257 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 36 e17 gpio pdi data[4] a0: siul_gpio[135] a1: flexpwm2_a[2] a2: _ a3: etimer1_etc[4] i: pdi_data[4] i: _ i: _ ? disabled pdi medium vdd_hv_pdi f1 gpio nexus mdo[6] 1 a0: siul_gpio[113] a1: _ a2: npc_wrapper_mdo[6] a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io f2 gpio nexus mdo[11] 1 a0: siul_gpio[108] a1: _ a2: npc_wrapper_mdo[11] a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io f3 gpio dspi1 sout a0: siul_gpio[7] a1: dspi1_sout a2: _ a3: _ i: _ i: _ i: siul_eirq[7] ? disabled gp slow/ medium vdd_hv_io f4 gpio dspi1 sin a0: siul_gpio[8] a1: _ a2: _ a3: _ i: dspi1_sin i: _ i: siul_eirq[8] ? disabled gp slow/ medium vdd_hv_io f14 gpio mc_cgl clk_out a0: siul_gpio[233] a1: mc_cgl_clk_out a2: etimer2_etc[5] a3: _ i: _ i: _ i: _ ? disabled pdi fast vdd_hv_pdi f15 gpio pdi data[6] a0: siul_gpio[137] a1: flexpwm2_b[0] a2: _ a3: etimer1_etc[1] i: pdi_data[6] i: _ i: _ ? disabled pdi medium vdd_hv_pdi f16 gpio pdi data[7] a0: siul_gpio[138] a1: flexpwm2_b[2] a2: _ a3: etimer1_etc[5] i: pdi_data[7] i: _ i: _ ? disabled pdi medium vdd_hv_pdi f17 gpio pdi data[8] a0: siul_gpio[139] a1: flexpwm2_a[3] a2: _ a3: _ i: pdi_data[8] i: _ i: _ ? disabled pdi medium vdd_hv_pdi table 9. 257 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
package pinouts and signal descriptions mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 37 g1 gpio nexus mdo[4] 1 a0: siul_gpio[115] a1: _ a2: npc_wrapper_mdo[4] a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io g3 gpio dspi0 sck a0: siul_gpio[37] a1: dspi0_sck a2: _ a3: sscm_debug[5] i: flexpwm0_fault[3] i: _ i: siul_eirq[23] ? disabled gp slow/ medium vdd_hv_io g4 gpio dspi1 sck a0: siul_gpio[6] a1: dspi1_sck a2: _ a3: _ i: _ i: _ i: siul_eirq[6] ? disabled gp slow/ medium vdd_hv_io g14 gpio pdi data[9] a0: siul_gpio[140] a1: flexpwm2_x[2] a2: _ a3: _ i: pdi_data[9] i: _ i: _ ? disabled pdi medium vdd_hv_pdi g15 gpio pdi data[10] a0: siul_gpio[141] a1: flexpwm2_x[3] a2: _ a3: _ i: pdi_data[10] i: _ i: _ ? disabled pdi medium vdd_hv_pdi g16 gpio pdi data[11] a0: siul_gpio[142] a1: flexpwm2_x[0] a2: _ a3: _ i: pdi_data[11] i: _ i: _ ? disabled pdi medium vdd_hv_pdi g17 gpio pdi frame_v a0: siul_gpio[130] a1: _ a2: _ a3: _ i: pdi_frame_v i: lin2_rxd i: flexpwm2_fault[1] ? disabled pdi medium vdd_hv_pdi h1 gpio nexus mdo[10] 1 a0: siul_gpio[109] a1: _ a2: npc_wrapper_mdo[10] a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io h3 gpio dspi0 cs0 a0: siul_gpio[36] a1: dspi0_cs0 a2: _ a3: sscm_debug[4] i: _ i: _ i: siul_eirq[22] ? disabled gp slow/ medium vdd_hv_io table 9. 257 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 38 h4 gpio dspi1 cs0 a0: siul_gpio[5] a1: dspi1_cs0 a2: _ a3: dspi0_cs7 i: _ i: _ i: siul_eirq[5] ? disabled gp slow/ medium vdd_hv_io h14 gpio pdi data[12] a0: siul_gpio[143] a1: _ a2: _ a3: _ i: pdi_data[12] i: lin3_rxd i: flexpwm2_fault[3] ? disabled pdi medium vdd_hv_pdi h15 gpio pdi data[13] a0: siul_gpio[144] a1: pdi_sens_sel[2] a2: ctu1_ext_tgr a3: _ i: pdi_data[13] i: _ i: _ ? disabled pdi medium vdd_hv_pdi h17 gpio flexpwm0 x[0] a0: siul_gpio[194] a1: flexpwm0_x[0] a2: ebi_d28 a3: _ i: _ i: _ i: _ ? disabled dram acc vdd_hv_io j1 gpio nexus mcko a0: siul_gpio[87] a1: _ a2: npc_wrapper_mcko a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io j2 gpio nexus mdo[8] 1 a0: siul_gpio[111] a1: _ a2: npc_wrapper_mdo[8] a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io j3 gpio dspi2 cs0 a0: siul_gpio[10] a1: dspi2_cs0 a2: _ a3: can3_txd i: _ i: _ i: siul_eirq[9] ? disabled gp slow/ medium vdd_hv_io j4 gpio dspi2 cs2 a0: siul_gpio[42] a1: dspi2_cs2 a2: lin3_txd a3: can2_txd i: flexpwm0_fault[1] i: _ i: _ ? disabled gp slow/ medium vdd_hv_io j14 gpio pdi data[14] a0: siul_gpio[145] a1: pdi_sens_sel[1] a2: i2c2_clock a3: _ i: pdi_data[14] i: _ i: _ ? disabled pdi medium vdd_hv_pdi table 9. 257 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
package pinouts and signal descriptions mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 39 j15 gpio pdi data[15] a0: siul_gpio[146] a1: pdi_sens_sel[0] a2: i2c2_data a3: _ i: pdi_data[15] i: ctu1_ext_in i: _ ? disabled pdi medium vdd_hv_pdi j17 gpio flexpwm0 x[1] a0: siul_gpio[195] a1: flexpwm0_x[1] a2: ebi_d29 a3: _ i: _ i: _ i: _ ? disabled dram acc vdd_hv_io k1 gpio nexus mseo_b[0] 1 a0: siul_gpio[89] a1: _ a2: npc_wrapper_mseo_b[0] a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io k2 gpio nexus mseo_b[1] 1 a0: siul_gpio[88] a1: _ a2: npc_wrapper_mseo_b[1] a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io k3 gpio nexus rdy_b a0: siul_gpio[216] a1: _ a2: nexus_rdy_b a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io k4 gpio dspi0 sin a0: siul_gpio[39] a1: _ a2: _ a3: sscm_debug[7] i: dspi0_sin i: _ i: _ ? disabled gp slow/ medium vdd_hv_io k14 gpio flexpwm0 x[2] a0: siul_gpio[196] a1: flexpwm0_x[2] a2: ebi_d30 a3: _ i: _ i: _ i: _ ? disabled dram acc vdd_hv_io k15 gpio flexpwm0 x[3] a0: siul_gpio[197] a1: flexpwm0_x[3] a2: ebi_d31 a3: _ i: _ i: _ i: _ ? disabled dram acc vdd_hv_io k16 gpio flexpwm0 a[1] a0: siul_gpio[149] a1: _ a2: ebi_rd_wr a3: flexpwm0_a[1] i: _ i: _ i: _ ? disabled dram acc vdd_hv_io table 9. 257 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 40 k17 gpio flexpwm0 b[0] a0: siul_gpio[148] a1: _ a2: ebi_clkout a3: flexpwm0_b[0] i: _ i: _ i: _ ? disabled dram acc vdd_hv_io l1 gpio nexus evto_b a0: siul_gpio[90] a1: _ a2: npc_wrapper_evto_b a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io l2 gpio nexus evti_b a0: siul_gpio[91] a1: _ a2: leo_sor_proxy_evti_b a3: _ i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io l3 gpio dspi2 sck a0: siul_gpio[11] a1: dspi2_sck a2: _ a3: _ i: can3_rxd i: _ i: siul_eirq[10] ? disabled gp slow/ medium vdd_hv_io l4 gpio nexus mdo[13] 1 a0: siul_gpio[218] a1: _ a2: npc_wrapper_mdo[13] a3: _ i: can2_rxd i: can3_rxd i: _ ? disabled gp slow/ fast vdd_hv_io l16 gpio flexpwm0 b[1] a0: siul_gpio[150] a1: dramc_cs0 a2: ebi_ts a3: flexpwm0_b[1] i: _ i: _ i: _ ? disabled dram acc vdd_hv_io l17 gpio tdo a0: siul_gpio[20] a1: jtagc_tdo a2: _ a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io m3 gpio dspi1 cs2 a0: siul_gpio[56] a1: dspi1_cs2 a2: _ a3: dspi0_cs5 i: flexpwm0_fault[3] i: lin2_rxd i: _ ? disabled gp slow/ medium vdd_hv_io m4 gpio nexus mdo[12] 1 a0: siul_gpio[217] a1: _ a2: npc_wrapper_mdo[12] a3: can2_txd i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io table 9. 257 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
package pinouts and signal descriptions mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 41 m14 gpio flexpwm0 b[2] a0: siul_gpio[152] a1: dramc_cas a2: ebi_we_be_1 a3: flexpwm0_b[2] i: _ i: _ i: _ ? disabled dram acc vdd_hv_io m15 gpio tdi a0: siul_gpio[21] a1: _ a2: _ a3: _ i: jtagc_tdi i: _ i: _ ? pull up gp slow/ medium vdd_hv_io m17 gpio flexpwm1 a[1] a0: siul_gpio[157] a1: dramc_odt a2: ebi_cs1 a3: flexpwm1_a[1] i: _ i: _ i: _ ? disabled dram acc vdd_hv_io n3 gpio dspi0 cs3 a0: siul_gpio[53] a1: dspi0_cs3 a2: i2c2_clock a3: _ i: flexpwm0_fault[2] i: _ i: _ ? disabled gp slow/ medium vdd_hv_io n14 gpio flexpwm0 b[3] a0: siul_gpio[154] a1: dramc_ba[0] a2: ebi_we_be_3 a3: flexpwm0_b[3] i: _ i: _ i: _ ? disabled dram acc vdd_hv_io n15 gpio flexpwm0 a[2] a0: siul_gpio[151] a1: dramc_ras a2: ebi_we_be_0 a3: flexpwm0_a[2] i: _ i: _ i: _ ? disabled dram acc vdd_hv_io n16 gpio flexpwm1 a[0] a0: siul_gpio[155] a1: dramc_ba[1] a2: ebi_bdip a3: flexpwm1_a[0] i: _ i: _ i: _ ? disabled dram acc vdd_hv_io n17 gpio flexpwm1 b[0] a0: siul_gpio[156] a1: dramc_ba[2] a2: ebi_cs0 a3: flexpwm1_b[0] i: _ i: _ i: _ ? disabled dram acc vdd_hv_io p3 gpio dspi0 cs2 a0: siul_gpio[54] a1: dspi0_cs2 a2: i2c2_data a3: _ i: flexpwm0_fault[1] i: _ i: _ ? disabled gp slow/ medium vdd_hv_io table 9. 257 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 42 p5 gpio etimer1 etc[1] a0: siul_gpio[45] a1: etimer1_etc[1] a2: _ a3: _ i: ctu0_ext_in i: flexpwm0_ext_sync i: ctu1_ext_in ? disabled gp slow/ medium vdd_hv_io p6 gpio etimer1 etc[2] a0: siul_gpio[46] a1: etimer1_etc[2] a2: ctu0_ext_tgr a3: _ i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io p7 ana adc0 an[0] ? siul_gpi[23] lin0_rxd an: adc0_an[0] analog vdd_hv_adr02 p8 gpio etimer1 etc[3] a0: siul_gpio[92] a1: etimer1_etc[3] a2: _ a3: _ i: ctu1_ext_in i: mc_rgm_fab i: siul_eirq[30] ? pull down gp slow/ medium vdd_hv_io p11 ana adc0_adc1 an[14] ? siul_gpi[28] an: adc0_adc1_an[14] analog shared vdd_hv_adr02 p12 gpio etimer1 etc[4] a0: siul_gpio[93] a1: etimer1_etc[4] a2: ctu1_ext_tgr a3: _ i: _ i: _ i: siul_eirq[31] ? disabled gp slow/ medium vdd_hv_io p13 gpio etimer1 etc[5] a0: siul_gpio[78] a1: etimer1_etc[5] a2: _ a3: _ i: _ i: _ i: siul_eirq[26] ? disabled gp slow/ medium vdd_hv_io p15 gpio flexpwm0 a[3] a0: siul_gpio[153] a1: dramc_web a2: ebi_we_be_2 a3: flexpwm0_a[3] i: _ i: _ i: _ ? disabled dram acc vdd_hv_io p16 gpio flexpwm0 a[0] a0: siul_gpio[147] a1: dramc_cke a2: ebi_oe a3: flexpwm0_a[0] i: _ i: _ i: _ ? disabled dram acc vdd_hv_io table 9. 257 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
package pinouts and signal descriptions mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 43 p17 gpio flexpwm1 b[1] a0: siul_gpio[163] a1: dramc_add[5] a2: ebi_add13 a3: flexpwm1_b[1] i: _ i: _ i: _ ? disabled dram acc vdd_hv_io r4 gpio dspi1 cs3 a0: siul_gpio[55] a1: dspi1_cs3 a2: lin2_txd a3: dspi0_cs4 i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io r5 ana adc2 an[0] ? siul_gpi[221] an: adc2_an[0] ? analog vdd_hv_adr02 r6 ana adc2 an[3] ? siul_gpi[224] an: adc2_an[3] ? analog vdd_hv_adr02 r8 ana adc2_adc3 an[14] ? siul_gpi[228] an: adc2_adc3_an[14] ? analog shared vdd_hv_adr13 r10 ana adc0 an[2] ? siul_gpi[33] an: adc0_an[2] ? analog vdd_hv_adr02 r11 ana adc0_adc1 an[13] ? siul_gpi[27] an: adc0_adc1_an[13] ? analog shared vdd_hv_adr02 r12 ana adc1 an[1] ? siul_gpi[30] etimer0_etc[4] siul_eirq[19] an: adc1_an[1] ? analog vdd_hv_adr13 r14 gpio lin0 txd a0: siul_gpio[18] a1: lin0_txd a2: i2c0_clock a3: sscm_debug[2] i: _ i: _ i: siul_eirq[17] ? disabled gp slow/ medium vdd_hv_io r16 gpio flexpwm1 a[2] a0: siul_gpio[164] a1: dramc_add[6] a2: ebi_add14 a3: flexpwm1_a[2] i: _ i: _ i: _ ? disabled dram acc vdd_hv_io table 9. 257 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 44 r17 gpio flexpwm1 b[2] a0: siul_gpio[165] a1: dramc_add[7] a2: ebi_add15 a3: flexpwm1_b[2] i: _ i: _ i: _ ? disabled dram acc vdd_hv_io t3 gpio dspi2 sout a0: siul_gpio[12] a1: dspi2_sout a2: _ a3: _ i: _ i: _ i: siul_eirq[11] ? disabled gp slow/ medium vdd_hv_io t4 ana adc3 an[0] ? siul_gpi[229] an: adc3_an[0] ? analog vdd_hv_adr13 t5 ana adc3 an[3] ? siul_gpi[232] an: adc3_an[3] ? analog vdd_hv_adr13 t6 ana adc2 an[2] ? siul_gpi[223] an: adc2_an[2] ? analog vdd_hv_adr02 t8 ana adc2_adc3 an[13] ? siul_gpi[227] an: adc2_adc3_an[13] ? analog shared vdd_hv_adr02 t10 ana adc0 an[1] ? siul_gpi[24] etimer0_etc[5] an: adc0_an[1] ? analog vdd_hv_adr02 t11 ana adc0_adc1 an[12] ? siul_gpi[26] an: adc0_adc1_an[12] ? analog shared vdd_hv_adr02 t12 ana adc1 an[0] ? siul_gpi[29] lin1_rxd an: adc1_an[0] ? analog vdd_hv_adr13 t13 ana adc1 an[2] ? siul_gpi[31] siul_eirq[20] an: adc1_an[2] ? analog vdd_hv_adr13 table 9. 257 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
package pinouts and signal descriptions mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 45 t14 gpio lin0 rxd a0: siul_gpio[19] a1: _ a2: i2c0_data a3: sscm_debug[3] i: lin0_rxd i: _ i: _ ? disabled gp slow/ medium vdd_hv_io t15 gpio etimer1 etc[0] a0: siul_gpio[4] a1: etimer1_etc[0] a2: _ a3: _ i: _ i: _ i: siul_eirq[4] ? disabled gp slow/ medium vdd_hv_io u3 gpio dspi2 sin a0: siul_gpio[13] a1: _ a2: _ a3: _ i: dspi2_sin i: flexpwm0_fault[0] i: siul_eirq[12] ? disabled gp slow/ medium vdd_hv_io u4 ana adc3 an[1] ? siul_gpi[230] an: adc3_an[1] ? analog vdd_hv_adr13 u5 ana adc3 an[2] ? siul_gpi[231] an: adc3_an[2] ? analog vdd_hv_adr13 u6 ana adc2 an[1] ? siul_gpi[222] an: adc2_an[1] ? analog vdd_hv_adr02 u7 ana adc2_adc3 an[11] ? siul_gpi[225] an: adc2_adc3_an[11] ? analog shared vdd_hv_adr13 u8 ana adc2_adc3 an[12] ? siul_gpi[226] an: adc2_adc3_an[12] ? analog shared vdd_hv_adr13 u11 ana adc0_adc1 an[11] ? siul_gpi[25] an: adc0_adc1_an[11] ? analog shared vdd_hv_adr02 end of 257 mapbga pin multiplexing table notes: 1 do not connect pin directly to a power supply or ground. table 9. 257 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 46 table 10. 473 mapbga pin multiplexing ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain a4 gpio nexus mdo[5] 1 a0: siul_gpio[114] a1: _ a2: npc_wrapper_mdo[5] a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io a5 gpio nexus mdo[7] 1 a0: siul_gpio[112] a1: _ a2: npc_wrapper_mdo[7] a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io a6 gpio nexus mdo[9] 1 a0: siul_gpio[110] a1: _ a2: npc_wrapper_mdo[9] a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io a7 gpio flexray cb_tx a0: siul_gpio[51] a1: flexray_cb_tx a2: _ a3: _ i: _ i: _ i: _ ? disabled gp slow/ symmetric vdd_hv_io a8 gpio flexray ca_tr_en a0: siul_gpio[47] a1: flexray_ca_tr_en a2: _ a3: _ i: ctu0_ext_in i: flexpwm0_ext_sync i: _ ? disabled gp slow/ symmetric vdd_hv_io a9 gpio fec rx_dv a0: siul_gpio[210] a1: flexray_dbg3 a2: etimer2_etc[0] a3: dspi0_cs7 i: fec_rx_dv i: _ i: _ ? disabled gp slow/ medium vdd_hv_io a10 gpio fec mdio a0: siul_gpio[198] a1: fec_mdio a2: _ a3: dspi2_cs0 i: _ i: _ i: siul_eirq[28] ? disabled gp slow/ medium vdd_hv_io a11 gpio fec tx_clk a0: siul_gpio[207] a1: flexray_dbg0 a2: etimer2_etc[4] a3: dspi0_cs4 i: fec_tx_clk i: _ i: _ ? disabled gp slow/ medium vdd_hv_io a12 gpio fec tx_en a0: siul_gpio[200] a1: fec_tx_en a2: _ a3: lin0_txd i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io
package pinouts and signal descriptions mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 47 a13 gpio fec txd[3] a0: siul_gpio[204] a1: fec_txd[3] a2: _ a3: dspi2_cs2 i: flexpwm1_fault[2] i: _ i: siul_eirq[29] ? disabled gp slow/ medium vdd_hv_io a15 gpio pdi data[3] a0: siul_gpio[134] a1: flexpwm2_x[1] a2: _ a3: _ i: pdi_data[3] i: _ i: _ ? disabled pdi medium vdd_hv_pdi a16 gpio pdi data[1] a0: siul_gpio[132] a1: flexpwm2_b[3] a2: _ a3: _ i: pdi_data[1] i: _ i: _ ? disabled pdi medium vdd_hv_pdi a17 gpio pdi clock a0: siul_gpio[128] a1: flexpwm2_b[1] a2: _ a3: etimer1_etc[3] i: pdi_clock i: _ i: _ ? disabled pdi medium vdd_hv_pdi a18 gpio pdi data[7] a0: siul_gpio[138] a1: flexpwm2_b[2] a2: _ a3: etimer1_etc[5] i: pdi_data[7] i: _ i: _ ? disabled pdi medium vdd_hv_pdi a19 gpio pdi data[10] a0: siul_gpio[141] a1: flexpwm2_x[3] a2: _ a3: _ i: pdi_data[10] i: _ i: _ ? disabled pdi medium vdd_hv_pdi a20 gpio pdi data[13] a0: siul_gpio[144] a1: pdi_sens_sel[2] a2: ctu1_ext_tgr a3: _ i: pdi_data[13] i: _ i: _ ? disabled pdi medium vdd_hv_pdi a21 gpio pdi data[15] a0: siul_gpio[146] a1: pdi_sens_sel[0] a2: i2c2_data a3: _ i: pdi_data[15] i: ctu1_ext_in i: _ ? disabled pdi medium vdd_hv_pdi b3 gpio mc_cgl clk_out a0: siul_gpio[22] a1: mc_cgl_clk_out a2: etimer2_etc[5] a3: _ i: _ i: _ i: siul_eirq[18] ? disabled gp slow/ fast vdd_hv_io table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 48 b4 gpio can1 txd a0: siul_gpio[14] a1: can1_txd a2: _ a3: _ i: _ i: _ i: siul_eirq[13] ? disabled gp slow/ medium vdd_hv_io b5 gpio nexus mdo[14] 1 a0: siul_gpio[219] a1: _ a2: npc_wrapper_mdo[14] a3: can3_txd i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io b6 gpio dspi2 cs1 a0: siul_gpio[9] a1: dspi2_cs1 a2: _ a3: _ i: flexpwm0_fault[0] i: lin3_rxd i: can2_rxd ? disabled gp slow/ medium vdd_hv_io b7 gpio flexray cb_tr_en a0: siul_gpio[52] a1: flexray_cb_tr_en a2: _ a3: _ i: _ i: _ i: _ ? disabled gp slow/ symmetric vdd_hv_io b8 gpio flexray ca_tx a0: siul_gpio[48] a1: flexray_ca_tx a2: _ a3: _ i: ctu1_ext_in i: _ i: _ ? disabled gp slow/ symmetric vdd_hv_io b9 gpio fec rxd[3] a0: siul_gpio[214] a1: i2c1_data a2: _ a3: _ i: fec_rxd[3] i: _ i: _ ? disabled gp slow/ medium vdd_hv_io b10 gpio fec rx_er a0: siul_gpio[215] a1: _ a2: _ a3: dspi0_cs1 i: fec_rx_er i: _ i: _ ? disabled gp slow/ medium vdd_hv_io b11 gpio fec txd[0] a0: siul_gpio[201] a1: fec_txd[0] a2: etimer2_etc[1] a3: _ i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io b12 gpio fec rxd[0] a0: siul_gpio[211] a1: i2c1_clock a2: _ a3: _ i: fec_rxd[0] i: _ i: siul_eirq[27] ? disabled gp slow/ medium vdd_hv_io table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
package pinouts and signal descriptions mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 49 b13 gpio fec tx_er a0: siul_gpio[205] a1: fec_tx_er a2: dspi2_cs3 a3: _ i: flexpwm1_fault[3] i: lin0_rxd i: _ ? disabled gp slow/ medium vdd_hv_io b15 gpio pdi data[6] a0: siul_gpio[137] a1: flexpwm2_b[0] a2: _ a3: etimer1_etc[1] i: pdi_data[6] i: _ i: _ ? disabled pdi medium vdd_hv_pdi b16 gpio pdi data[4] a0: siul_gpio[135] a1: flexpwm2_a[2] a2: _ a3: etimer1_etc[4] i: pdi_data[4] i: _ i: _ ? disabled pdi medium vdd_hv_pdi b17 gpio pdi data[0] a0: siul_gpio[131] a1: _ a2: lin3_txd a3: _ i: pdi_data[0] i: _ i: flexpwm2_fault[2] ? disabled pdi medium vdd_hv_pdi b18 gpio pdi line_v a0: siul_gpio[129] a1: _ a2: lin2_txd a3: _ i: pdi_line_v i: _ i: flexpwm2_fault[0] ? disabled pdi medium vdd_hv_pdi b19 gpio pdi data[9] a0: siul_gpio[140] a1: flexpwm2_x[2] a2: _ a3: _ i: pdi_data[9] i: _ i: _ ? disabled pdi medium vdd_hv_pdi b20 gpio pdi data[14] a0: siul_gpio[145] a1: pdi_sens_sel[1] a2: i2c2_clock a3: _ i: pdi_data[14] i: _ i: _ ? disabled pdi medium vdd_hv_pdi b21 gpio can0 txd a0: siul_gpio[16] a1: can0_txd a2: _ a3: sscm_debug[0] i: _ i: _ i: siul_eirq[15] ? disabled gp slow/ medium vdd_hv_io c2 gpio nexus mdo[15] 1 a0: siul_gpio[220] a1: _ a2: npc_wrapper_mdo[15] a3: _ i: can3_rxd i: can2_rxd i: _ ? disabled gp slow/ fast vdd_hv_io table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 50 c5 gpio flexray cb_rx a0: siul_gpio[50] a1: _ a2: ctu1_ext_tgr a3: _ i: flexray_cb_rx i: _ i: _ ? disabled gp slow/ medium vdd_hv_io c6 gpio etimer0 etc[4] a0: siul_gpio[43] a1: etimer0_etc[4] a2: _ a3: _ i: _ i: mc_rgm_abs[0] i: _ ? pull down gp slow/ medium vdd_hv_io c7 gpio etimer0 etc[1] a0: siul_gpio[1] a1: etimer0_etc[1] a2: _ a3: _ i: _ i: _ i: siul_eirq[1] ? disabled gp slow/ medium vdd_hv_io c8 gpio etimer0 etc[2] a0: siul_gpio[2] a1: etimer0_etc[2] a2: _ a3: _ i: _ i: _ i: siul_eirq[2] ? disabled gp slow/ medium vdd_hv_io c9 gpio etimer0 etc[3] a0: siul_gpio[3] a1: etimer0_etc[3] a2: _ a3: _ i: _ i: mc_rgm_abs[2] i: siul_eirq[3] ? pull down gp slow/ medium vdd_hv_io c10 gpio fec txd[2] a0: siul_gpio[203] a1: fec_txd[2] a2: _ a3: _ i: flexpwm1_fault[1] i: _ i: _ ? disabled gp slow/ medium vdd_hv_io c11 gpio fec txd[1] a0: siul_gpio[202] a1: fec_txd[1] a2: _ a3: dspi2_sck i: flexpwm1_fault[0] i: _ i: _ ? disabled gp slow/ medium vdd_hv_io c12 gpio fec crs a0: siul_gpio[208] a1: flexray_dbg1 a2: etimer2_etc[3] a3: dspi0_cs5 i: fec_crs i: _ i: _ ? disabled gp slow/ medium vdd_hv_io c13 gpio fec rx_clk a0: siul_gpio[209] a1: flexray_dbg2 a2: etimer2_etc[2] a3: dspi0_cs6 i: fec_rx_clk i: _ i: siul_eirq[25] ? disabled gp slow/ medium vdd_hv_io table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
package pinouts and signal descriptions mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 51 c14 gpio fec rxd[1] a0: siul_gpio[212] a1: dspi1_cs1 a2: etimer2_etc[5] a3: _ i: fec_rxd[1] i: _ i: _ ? disabled gp slow/ medium vdd_hv_io c15 gpio fec col a0: siul_gpio[206] a1: fec_col a2: _ a3: lin1_txd i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io c16 gpio pdi data[5] a0: siul_gpio[136] a1: flexpwm2_a[0] a2: _ a3: etimer1_etc[0] i: pdi_data[5] i: _ i: _ ? disabled pdi medium vdd_hv_pdi c17 gpio pdi data[2] a0: siul_gpio[133] a1: flexpwm2_a[1] a2: _ a3: etimer1_etc[2] i: pdi_data[2] i: _ i: _ ? disabled pdi medium vdd_hv_pdi c18 gpio pdi data[8] a0: siul_gpio[139] a1: flexpwm2_a[3] a2: _ a3: _ i: pdi_data[8] i: _ i: _ ? disabled pdi medium vdd_hv_pdi c19 gpio pdi data[12] a0: siul_gpio[143] a1: _ a2: _ a3: _ i: pdi_data[12] i: lin3_rxd i: flexpwm2_fault[3] ? disabled pdi medium vdd_hv_pdi c20 gpio can0 rxd a0: siul_gpio[17] a1: _ a2: _ a3: sscm_debug[1] i: can0_rxd i: can1_rxd i: siul_eirq[16] ? disabled gp slow/ medium vdd_hv_io c22 gpio siul gpio[197] a0: siul_gpio[197] a1: flexpwm0_x[3] a2: ebi_d31 a3: _ i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram c23 gpio dramc cas a0: siul_gpio[152] a1: dramc_cas a2: ebi_we_be_1 a3: flexpwm0_b[2] i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 52 d1 gpio nexus mdo[1] 1 a0: siul_gpio[86] a1: _ a2: npc_wrapper_mdo[1] a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io d2 gpio nexus mdo[3] 1 a0: siul_gpio[84] a1: _ a2: npc_wrapper_mdo[3] a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io d3 gpio can1 rxd a0: siul_gpio[15] a1: _ a2: _ a3: _ i: can1_rxd i: can0_rxd i: siul_eirq[14] ? disabled gp slow/ medium vdd_hv_io d4 gpio dspi0 sout a0: siul_gpio[38] a1: dspi0_sout a2: _ a3: sscm_debug[6] i: _ i: _ i: siul_eirq[24] ? disabled gp slow/ medium vdd_hv_io d6 gpio etimer0 etc[5] a0: siul_gpio[44] a1: etimer0_etc[5] a2: _ a3: _ i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io d7 gpio etimer0 etc[0] a0: siul_gpio[0] a1: etimer0_etc[0] a2: _ a3: _ i: dspi2_sin i: _ i: siul_eirq[0] ? disabled gp slow/ medium vdd_hv_io d14 gpio fec rxd[2] a0: siul_gpio[213] a1: _ a2: _ a3: dspi2_sout i: fec_rxd[2] i: _ i: siul_eirq[21] ? disabled gp slow/ medium vdd_hv_io d15 gpio fec mdc a0: siul_gpio[199] a1: fec_mdc a2: _ a3: _ i: _ i: lin1_rxd i: _ ? disabled gp slow/ medium vdd_hv_io d18 gpio pdi data[11] a0: siul_gpio[142] a1: flexpwm2_x[0] a2: _ a3: _ i: pdi_data[11] i: _ i: _ ? disabled pdi medium vdd_hv_pdi table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
package pinouts and signal descriptions mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 53 d19 gpio pdi frame_v a0: siul_gpio[130] a1: _ a2: _ a3: _ i: pdi_frame_v i: lin2_rxd i: flexpwm2_fault[1] ? disabled pdi medium vdd_hv_pdi d21 gpio dramc ba[1] a0: siul_gpio[155] a1: dramc_ba[1] a2: ebi_bdip a3: flexpwm1_a[0] i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram d22 gpio siul gpio[195] a0: siul_gpio[195] a1: flexpwm0_x[1] a2: ebi_d29 a3: _ i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram d23 gpio dramc ba[0] a0: siul_gpio[154] a1: dramc_ba[0] a2: ebi_we_be_3 a3: flexpwm0_b[3] i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram e2 gpio nexus mdo[2] 1 a0: siul_gpio[85] a1: _ a2: npc_wrapper_mdo[2] a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io e3 gpio flexray ca_rx a0: siul_gpio[49] a1: _ a2: ctu0_ext_tgr a3: _ i: flexray_ca_rx i: _ i: _ ? disabled gp slow/ medium vdd_hv_io e20 gpio mc_cgl clk_out a0: siul_gpio[233] a1: mc_cgl_clk_out a2: etimer2_etc[5] a3: _ i: _ i: _ i: _ ? disabled pdi fast vdd_hv_pdi e21 gpio siul gpio[149] a0: siul_gpio[149] a1: _ a2: ebi_rd_wr a3: flexpwm0_a[1] i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram e22 gpio dramc cs0 a0: siul_gpio[150] a1: dramc_cs0 a2: ebi_ts a3: flexpwm0_b[1] i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 54 e23 gpio dramc ba[2] a0: siul_gpio[156] a1: dramc_ba[2] a2: ebi_cs0 a3: flexpwm1_b[0] i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram f1 gpio nexus mdo[10] 1 a0: siul_gpio[109] a1: _ a2: npc_wrapper_mdo[10] a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io f2 gpio nexus mdo[11] 1 a0: siul_gpio[108] a1: _ a2: npc_wrapper_mdo[11] a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io f3 gpio nexus mdo[6] 1 a0: siul_gpio[113] a1: _ a2: npc_wrapper_mdo[6] a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io f4 gpio nexus mdo[4] 1 a0: siul_gpio[115] a1: _ a2: npc_wrapper_mdo[4] a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io f20 gpio dramc ras a0: siul_gpio[151] a1: dramc_ras a2: ebi_we_be_0 a3: flexpwm0_a[2] i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram f21 gpio siul gpio[194] a0: siul_gpio[194] a1: flexpwm0_x[0] a2: ebi_d28 a3: _ i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram f22 gpio siul gpio[148] a0: siul_gpio[148] a1: _ a2: ebi_clkout a3: flexpwm0_b[0] i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram f23 gpio dramc d[5] a0: siul_gpio[179] a1: dramc_d[5] a2: ebi_d13 a3: ebi_add29 i: _ i: _ i: _ ? disabled dram dq vdd_hv_dram table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
package pinouts and signal descriptions mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 55 g1 gpio nexus mcko a0: siul_gpio[87] a1: _ a2: npc_wrapper_mcko a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io g3 gpio nexus mdo[8] 1 a0: siul_gpio[111] a1: _ a2: npc_wrapper_mdo[8] a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io g4 gpio nexus mseo_b[1] 1 a0: siul_gpio[88] a1: _ a2: npc_wrapper_mseo_b[1] a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io g20 gpio siul gpio[196] a0: siul_gpio[196] a1: flexpwm0_x[2] a2: ebi_d30 a3: _ i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram g21 gpio dramc dqs[0] a0: siul_gpio[190] a1: dramc_dqs[0] a2: ebi_d24 a3: _ i: _ i: _ i: _ ? disabled dram dq vdd_hv_dram g22 gpio dramc dm[0] a0: siul_gpio[192] a1: dramc_dm[0] a2: ebi_d26 a3: _ i: _ i: _ i: _ ? disabled dram dq vdd_hv_dram g23 gpio dramc d[7] a0: siul_gpio[181] a1: dramc_d[7] a2: ebi_d15 a3: ebi_add31 i: _ i: _ i: _ ? disabled dram dq vdd_hv_dram h1 gpio nexus evto_b a0: siul_gpio[90] a1: _ a2: npc_wrapper_evto_b a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io h3 gpio nexus mseo_b[0] 1 a0: siul_gpio[89] a1: _ a2: npc_wrapper_mseo_b[0] a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 56 h4 gpio nexus evti_b a0: siul_gpio[91] a1: _ a2: leo_sor_proxy_evti_b a3: _ i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io h20 gpio dramc d[2] a0: siul_gpio[176] a1: dramc_d[2] a2: ebi_d10 a3: ebi_add26 i: _ i: _ i: _ ? disabled dram dq vdd_hv_dram j1 gpio nexus rdy_b a0: siul_gpio[216] a1: _ a2: nexus_rdy_b a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io j2 gpio nexus mdo[13] 1 a0: siul_gpio[218] a1: _ a2: npc_wrapper_mdo[13] a3: _ i: can2_rxd i: can3_rxd i: _ ? disabled gp slow/ fast vdd_hv_io j3 gpio nexus mdo[12] 1 a0: siul_gpio[217] a1: _ a2: npc_wrapper_mdo[12] a3: can2_txd i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io j4 gpio dspi1 sin a0: siul_gpio[8] a1: _ a2: _ a3: _ i: dspi1_sin i: _ i: siul_eirq[8] ? disabled gp slow/ medium vdd_hv_io j20 gpio dramc d[0] a0: siul_gpio[174] a1: dramc_d[0] a2: ebi_d8 a3: ebi_add24 i: _ i: _ i: _ ? disabled dram dq vdd_hv_dram j21 gpio dramc d[1] a0: siul_gpio[175] a1: dramc_d[1] a2: ebi_d9 a3: ebi_add25 i: _ i: _ i: _ ? disabled dram dq vdd_hv_dram j22 gpio dramc d[3] a0: siul_gpio[177] a1: dramc_d[3] a2: ebi_d11 a3: ebi_add27 i: _ i: _ i: _ ? disabled dram dq vdd_hv_dram table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
package pinouts and signal descriptions mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 57 j23 gpio dramc d[6] a0: siul_gpio[180] a1: dramc_d[6] a2: ebi_d14 a3: ebi_add30 i: _ i: _ i: _ ? disabled dram dq vdd_hv_dram k1 gpio dspi0 sck a0: siul_gpio[37] a1: dspi0_sck a2: _ a3: sscm_debug[5] i: flexpwm0_fault[3] i: _ i: siul_eirq[23] ? disabled gp slow/ medium vdd_hv_io k2 gpio dspi1 cs0 a0: siul_gpio[5] a1: dspi1_cs0 a2: _ a3: dspi0_cs7 i: _ i: _ i: siul_eirq[5] ? disabled gp slow/ medium vdd_hv_io k3 gpio dspi1 sck a0: siul_gpio[6] a1: dspi1_sck a2: _ a3: _ i: _ i: _ i: siul_eirq[6] ? disabled gp slow/ medium vdd_hv_io k4 gpio dspi1 sout a0: siul_gpio[7] a1: dspi1_sout a2: _ a3: _ i: _ i: _ i: siul_eirq[7] ? disabled gp slow/ medium vdd_hv_io k21 gpio dramc d[4] a0: siul_gpio[178] a1: dramc_d[4] a2: ebi_d12 a3: ebi_add28 i: _ i: _ i: _ ? disabled dram dq vdd_hv_dram k22 gpio dramc d[8] a0: siul_gpio[182] a1: dramc_d[8] a2: ebi_d16 a3: _ i: _ i: _ i: _ ? disabled dram dq vdd_hv_dram k23 gpio dramc d[9] a0: siul_gpio[183] a1: dramc_d[9] a2: ebi_d17 a3: _ i: _ i: _ i: _ ? disabled dram dq vdd_hv_dram l1 gpio dspi0 cs0 a0: siul_gpio[36] a1: dspi0_cs0 a2: _ a3: sscm_debug[4] i: _ i: _ i: siul_eirq[22] ? disabled gp slow/ medium vdd_hv_io table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 58 l2 gpio dspi2 cs2 a0: siul_gpio[42] a1: dspi2_cs2 a2: lin3_txd a3: can2_txd i: flexpwm0_fault[1] i: _ i: _ ? disabled gp slow/ medium vdd_hv_io l3 gpio dspi2 cs0 a0: siul_gpio[10] a1: dspi2_cs0 a2: _ a3: can3_txd i: _ i: _ i: siul_eirq[9] ? disabled gp slow/ medium vdd_hv_io m1 gpio flexpwm0 x[0] a0: siul_gpio[57] a1: flexpwm0_x[0] a2: lin2_txd a3: _ i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io m3 gpio dspi0 sin a0: siul_gpio[39] a1: _ a2: _ a3: sscm_debug[7] i: dspi0_sin i: _ i: _ ? disabled gp slow/ medium vdd_hv_io m20 gpio dramc odt a0: siul_gpio[157] a1: dramc_odt a2: ebi_cs1 a3: flexpwm1_a[1] i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram m21 gpio dramc web a0: siul_gpio[153] a1: dramc_web a2: ebi_we_be_2 a3: flexpwm0_a[3] i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram m22 gpio dramc d[11] a0: siul_gpio[185] a1: dramc_d[11] a2: ebi_d19 a3: _ i: _ i: _ i: _ ? disabled dram dq vdd_hv_dram m23 gpio dramc d[10] a0: siul_gpio[184] a1: dramc_d[10] a2: ebi_d18 a3: _ i: _ i: _ i: _ ? disabled dram dq vdd_hv_dram n1 gpio flexpwm0 a[0] a0: siul_gpio[58] a1: flexpwm0_a[0] a2: _ a3: _ i: _ i: etimer0_etc[0] i: _ ? disabled gp slow/ medium vdd_hv_io table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
package pinouts and signal descriptions mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 59 n3 gpio flexpwm0 x[1] a0: siul_gpio[60] a1: flexpwm0_x[1] a2: _ a3: _ i: lin2_rxd i: _ i: _ ? disabled gp slow/ medium vdd_hv_io n4 gpio flexpwm0 b[2] a0: siul_gpio[100] a1: flexpwm0_b[2] a2: _ a3: _ i: _ i: etimer0_etc[5] i: _ ? disabled gp slow/ medium vdd_hv_io n20 gpio dramc dqs[1] a0: siul_gpio[191] a1: dramc_dqs[1] a2: ebi_d25 a3: _ i: _ i: _ i: _ ? disabled dram dq vdd_hv_dram n21 gpio dramc dm[1] a0: siul_gpio[193] a1: dramc_dm[1] a2: ebi_d27 a3: _ i: _ i: _ i: _ ? disabled dram dq vdd_hv_dram n22 gpio dramc d[13] a0: siul_gpio[187] a1: dramc_d[13] a2: ebi_d21 a3: _ i: _ i: _ i: _ ? disabled dram dq vdd_hv_dram n23 gpio dramc d[12] a0: siul_gpio[186] a1: dramc_d[12] a2: ebi_d20 a3: _ i: _ i: _ i: _ ? disabled dram dq vdd_hv_dram p1 gpio flexpwm0 b[0] a0: siul_gpio[59] a1: flexpwm0_b[0] a2: _ a3: _ i: _ i: etimer0_etc[1] i: _ ? disabled gp slow/ medium vdd_hv_io p2 gpio flexpwm0 b[1] a0: siul_gpio[62] a1: flexpwm0_b[1] a2: _ a3: _ i: _ i: etimer0_etc[3] i: _ ? disabled gp slow/ medium vdd_hv_io p3 gpio flexpwm0 a[2] a0: siul_gpio[99] a1: flexpwm0_a[2] a2: _ a3: _ i: _ i: etimer0_etc[4] i: _ ? disabled gp slow/ medium vdd_hv_io table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 60 p4 gpio flexpwm0 a[3] a0: siul_gpio[102] a1: flexpwm0_a[3] a2: _ a3: _ i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io p20 gpio dramc d[14] a0: siul_gpio[188] a1: dramc_d[14] a2: ebi_d22 a3: _ i: _ i: _ i: _ ? disabled dram dq vdd_hv_dram p21 gpio dramc d[15] a0: siul_gpio[189] a1: dramc_d[15] a2: ebi_d23 a3: _ i: _ i: _ i: _ ? disabled dram dq vdd_hv_dram r1 gpio flexpwm0 x[2] a0: siul_gpio[98] a1: flexpwm0_x[2] a2: lin3_txd a3: _ i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io r2 gpio flexpwm0 x[3] a0: siul_gpio[101] a1: flexpwm0_x[3] a2: _ a3: _ i: lin3_rxd i: _ i: _ ? disabled gp slow/ medium vdd_hv_io r3 gpio flexpwm0 a[1] a0: siul_gpio[80] a1: flexpwm0_a[1] a2: _ a3: _ i: _ i: etimer0_etc[2] i: _ ? disabled gp slow/ medium vdd_hv_io r21 gpio dramc add[3] a0: siul_gpio[161] a1: dramc_add[3] a2: ebi_add11 a3: ebi_tea i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram r22 gpio dramc cke a0: siul_gpio[147] a1: dramc_cke a2: ebi_oe a3: flexpwm0_a[0] i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram t1 gpio flexpwm0 b[3] a0: siul_gpio[103] a1: flexpwm0_b[3] a2: _ a3: _ i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
package pinouts and signal descriptions mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 61 t2 gpio flexpwm1 a[0] a0: siul_gpio[117] a1: flexpwm1_a[0] a2: _ a3: can2_txd i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io t3 gpio flexpwm1 a[1] a0: siul_gpio[120] a1: flexpwm1_a[1] a2: _ a3: can3_txd i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io t20 gpio dramc add[8] a0: siul_gpio[166] a1: dramc_add[8] a2: ebi_d0 a3: ebi_add16 i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram t21 gpio dramc add[9] a0: siul_gpio[167] a1: dramc_add[9] a2: ebi_d1 a3: ebi_add17 i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram t22 gpio dramc add[1] a0: siul_gpio[159] a1: dramc_add[1] a2: ebi_add9 a3: ebi_cs3 i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram u1 gpio flexpwm1 b[0] a0: siul_gpio[118] a1: flexpwm1_b[0] a2: _ a3: _ i: can2_rxd i: can3_rxd i: _ ? disabled gp slow/ medium vdd_hv_io u2 gpio flexpwm1 b[1] a0: siul_gpio[121] a1: flexpwm1_b[1] a2: _ a3: _ i: can3_rxd i: can2_rxd i: _ ? disabled gp slow/ medium vdd_hv_io u3 gpio flexpwm1 a[2] a0: siul_gpio[123] a1: flexpwm1_a[2] a2: _ a3: _ i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io u4 gpio dspi2 sck a0: siul_gpio[11] a1: dspi2_sck a2: _ a3: _ i: can3_rxd i: _ i: siul_eirq[10] ? disabled gp slow/ medium vdd_hv_io table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 62 u20 gpio dramc add[6] a0: siul_gpio[164] a1: dramc_add[6] a2: ebi_add14 a3: flexpwm1_a[2] i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram u21 gpio dramc add[12] a0: siul_gpio[170] a1: dramc_add[12] a2: ebi_d4 a3: ebi_add20 i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram u23 gpio dramc add[0] a0: siul_gpio[158] a1: dramc_add[0] a2: ebi_add8 a3: ebi_cs2 i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram v3 gpio flexpwm1 b[2] a0: siul_gpio[124] a1: flexpwm1_b[2] a2: _ a3: _ i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io v4 gpio dspi1 cs2 a0: siul_gpio[56] a1: dspi1_cs2 a2: _ a3: dspi0_cs5 i: flexpwm0_fault[3] i: lin2_rxd i: _ ? disabled gp slow/ medium vdd_hv_io v20 gpio lin0 txd a0: siul_gpio[18] a1: lin0_txd a2: i2c0_clock a3: sscm_debug[2] i: _ i: _ i: siul_eirq[17] ? disabled gp slow/ medium vdd_hv_io v21 gpio dramc add[13] a0: siul_gpio[171] a1: dramc_add[13] a2: ebi_d5 a3: ebi_add21 i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram v23 gpio dramc add[2] a0: siul_gpio[160] a1: dramc_add[2] a2: ebi_add10 a3: ebi_ta i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram w3 gpio dspi0 cs3 a0: siul_gpio[53] a1: dspi0_cs3 a2: i2c2_clock a3: _ i: flexpwm0_fault[2] i: _ i: _ ? disabled gp slow/ medium vdd_hv_io table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
package pinouts and signal descriptions mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 63 w20 gpio lin0 rxd a0: siul_gpio[19] a1: _ a2: i2c0_data a3: sscm_debug[3] i: lin0_rxd i: _ i: _ ? disabled gp slow/ medium vdd_hv_io w21 gpio dramc add[14] a0: siul_gpio[172] a1: dramc_add[14] a2: ebi_d6 a3: ebi_add22 i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram w22 gpio dramc add[7] a0: siul_gpio[165] a1: dramc_add[7] a2: ebi_add15 a3: flexpwm1_b[2] i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram w23 gpio dramc add[4] a0: siul_gpio[162] a1: dramc_add[4] a2: ebi_add12 a3: ebi_ale i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram y3 gpio dspi0 cs2 a0: siul_gpio[54] a1: dspi0_cs2 a2: i2c2_data a3: _ i: flexpwm0_fault[1] i: _ i: _ ? disabled gp slow/ medium vdd_hv_io y5 gpio flexpwm1 x[0] a0: siul_gpio[116] a1: flexpwm1_x[0] a2: etimer2_etc[0] a3: dspi0_cs1 i: ctu0_ext_in i: ctu1_ext_in i: _ ? disabled gp slow/ medium vdd_hv_io y6 ana adc3 an[0] ? siul_gpi[229] an: adc3_an[0] ? analog vdd_hv_adr23 y7 ana adc2_adc3 an[11] ? siul_gpi[225] an: adc2_adc3_an[11] ? analog shared vdd_hv_adr23 y8 ana adc2_adc3 an[14] ? siul_gpi[228] an: adc2_adc3_an[14] ? analog shared vdd_hv_adr23 table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 64 y9 gpio etimer1 etc[1] a0: siul_gpio[45] a1: etimer1_etc[1] a2: _ a3: _ i: ctu0_ext_in i: flexpwm0_ext_sync i: ctu1_ext_in ? disabled gp slow/ medium vdd_hv_io y10 gpio etimer1 etc[2] a0: siul_gpio[46] a1: etimer1_etc[2] a2: ctu0_ext_tgr a3: _ i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io y11 gpio etimer1 etc[3] a0: siul_gpio[92] a1: etimer1_etc[3] a2: _ a3: _ i: ctu1_ext_in i: mc_rgm_fab i: siul_eirq[30] ? pull down gp slow/ medium vdd_hv_io y14 ana adc0_adc1 an[11] ? siul_gpi[25] an: adc0_adc1_an[11] ? analog shared vdd_hv_adr0 y15 gpio etimer1 etc[5] a0: siul_gpio[78] a1: etimer1_etc[5] a2: _ a3: _ i: _ i: _ i: siul_eirq[26] ? disabled gp slow/ medium vdd_hv_io y16 gpio etimer1 etc[4] a0: siul_gpio[93] a1: etimer1_etc[4] a2: ctu1_ext_tgr a3: _ i: _ i: _ i: siul_eirq[31] ? disabled gp slow/ medium vdd_hv_io y17 ana adc1 an[8] ? siul_gpi[74] an: adc1_an[8] ? analog vdd_hv_adr1 y18 ana adc1 an[6] ? siul_gpi[76] an: adc1_an[6] ? analog vdd_hv_adr1 y21 gpio dramc add[15] a0: siul_gpio[173] a1: dramc_add[15] a2: ebi_d7 a3: ebi_add23 i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
package pinouts and signal descriptions mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 65 y22 gpio dramc add[11] a0: siul_gpio[169] a1: dramc_add[11] a2: ebi_d3 a3: ebi_add19 i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram y23 gpio dramc add[5] a0: siul_gpio[163] a1: dramc_add[5] a2: ebi_add13 a3: flexpwm1_b[1] i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram aa4 gpio dspi1 cs3 a0: siul_gpio[55] a1: dspi1_cs3 a2: lin2_txd a3: dspi0_cs4 i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io aa5 gpio flexpwm1 x[1] a0: siul_gpio[119] a1: flexpwm1_x[1] a2: etimer2_etc[1] a3: dspi0_cs4 i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io aa6 ana adc3 an[1] ? siul_gpi[230] an: adc3_an[1] ? analog vdd_hv_adr23 aa7 ana adc2_adc3 an[12] ? siul_gpi[226] an: adc2_adc3_an[12] ? analog shared vdd_hv_adr23 aa8 ana adc2 an[0] ? siul_gpi[221] an: adc2_an[0] ? analog vdd_hv_adr23 aa11 ana adc0 an[2] ? siul_gpi[33] an: adc0_an[2] ? analog vdd_hv_adr0 aa12 ana adc0 an[5] ? siul_gpi[66] an: adc0_an[5] ? analog vdd_hv_adr0 aa13 ana adc0 an[8] ? siul_gpi[69] an: adc0_an[8] ? analog vdd_hv_adr0 table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 66 aa14 ana adc0_adc1 an[12] ? siul_gpi[26] an: adc0_adc1_an[12] ? analog shared vdd_hv_adr0 aa15 ana adc1 an[0] ? siul_gpi[29] lin1_rxd an: adc1_an[0] ? analog vdd_hv_adr1 aa16 ana adc1 an[2] ? siul_gpi[31] siul_eirq[20] an: adc1_an[2] ? analog vdd_hv_adr1 aa17 ana adc1 an[5] ? siul_gpi[64] an: adc1_an[5] ? analog vdd_hv_adr1 aa18 ana adc1 an[7] ? siul_gpi[73] an: adc1_an[7] ? analog vdd_hv_adr1 aa19 gpio tdi a0: siul_gpio[21] a1: _ a2: _ a3: _ i: jtagc_tdi i: _ i: _ ? pull up gp slow/ medium vdd_hv_io aa20 gpio etimer1 etc[0] a0: siul_gpio[4] a1: etimer1_etc[0] a2: _ a3: _ i: _ i: _ i: siul_eirq[4] ? disabled gp slow/ medium vdd_hv_io aa22 gpio lin1 txd a0: siul_gpio[94] a1: lin1_txd a2: i2c1_clock a3: _ i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io aa23 gpio dramc add[10] a0: siul_gpio[168] a1: dramc_add[10] a2: ebi_d2 a3: ebi_add18 i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram ab3 gpio dspi2 sout a0: siul_gpio[12] a1: dspi2_sout a2: _ a3: _ i: _ i: _ i: siul_eirq[11] ? disabled gp slow/ medium vdd_hv_io table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
package pinouts and signal descriptions mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 67 ab4 gpio flexpwm1 x[2] a0: siul_gpio[122] a1: flexpwm1_x[2] a2: etimer2_etc[2] a3: dspi0_cs5 i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io ab5 gpio flexpwm1 x[3] a0: siul_gpio[125] a1: flexpwm1_x[3] a2: etimer2_etc[3] a3: dspi0_cs6 i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io ab6 ana adc3 an[2] ? siul_gpi[231] an: adc3_an[2] ? analog vdd_hv_adr23 ab7 ana adc2_adc3 an[13] ? siul_gpi[227] an: adc2_adc3_an[13] ? analog shared vdd_hv_adr23 ab8 ana adc2 an[1] ? siul_gpi[222] an: adc2_an[1] ? analog vdd_hv_adr23 ab9 ana adc2 an[2] ? siul_gpi[223] an: adc2_an[2] ? analog vdd_hv_adr23 ab10 ana adc0 an[0] ? siul_gpi[23] lin0_rxd an: adc0_an[0] ? analog vdd_hv_adr0 ab11 ana adc0 an[4] ? siul_gpi[70] an: adc0_an[4] ? analog vdd_hv_adr0 ab12 ana adc0 an[6] ? siul_gpi[71] an: adc0_an[6] ? analog vdd_hv_adr0 ab13 ana adc0 an[7] ? siul_gpi[68] an: adc0_an[7] ? analog vdd_hv_adr0 ab14 ana adc0_adc1 an[13] ? siul_gpi[27] an: adc0_adc1_an[13] ? analog shared vdd_hv_adr0 table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 68 ab15 ana adc1 an[1] ? siul_gpi[30] etimer0_etc[4] siul_eirq[19] an: adc1_an[1] ? analog vdd_hv_adr1 ab16 ana adc1 an[3] ? siul_gpi[32] an: adc1_an[3] ? analog vdd_hv_adr1 ab17 ana adc1 an[4] ? siul_gpi[75] an: adc1_an[4] ? analog vdd_hv_adr1 ab18 gpio tdo a0: siul_gpio[20] a1: jtagc_tdo a2: _ a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io ab21 gpio lin1 rxd a0: siul_gpio[95] a1: _ a2: i2c1_data a3: _ i: lin1_rxd i: _ i: _ ? disabled gp slow/ medium vdd_hv_io ac3 gpio dspi2 sin a0: siul_gpio[13] a1: _ a2: _ a3: _ i: dspi2_sin i: flexpwm0_fault[0] i: siul_eirq[12] ? disabled gp slow/ medium vdd_hv_io ac4 gpio flexpwm1 a[3] a0: siul_gpio[126] a1: flexpwm1_a[3] a2: etimer2_etc[4] a3: dspi0_cs7 i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io ac5 gpio flexpwm1 b[3] a0: siul_gpio[127] a1: flexpwm1_b[3] a2: etimer2_etc[5] a3: _ i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io ac6 ana adc3 an[3] ? siul_gpi[232] an: adc3_an[3] ?gp slow/ medium vdd_hv_adr23 ac9 ana adc2 an[3] ? siul_gpi[224] an: adc2_an[3] ? analog vdd_hv_adr23 table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
package pinouts and signal descriptions mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 69 ac10 ana adc0 an[1] ? siul_gpi[24] etimer0_etc[5] an: adc0_an[1] ? analog vdd_hv_adr0 ac11 ana adc0 an[3] ? siul_gpi[34] an: adc0_an[3] ? analog vdd_hv_adr0 ac14 ana adc0_adc1 an[14] ? siul_gpi[28] an: adc0_adc1_an[14] ? analog shared vdd_hv_adr0 end of 473 mapbga pin multiplexing table notes: 1 do not connect pin directly to a power supply or ground. table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice electrical characteristics freescale semiconductor 70 3 electrical characteristics 3.1 introduction this section contains detailed information on power c onsiderations, dc/ac electric al characteristics, and ac timing specifications for this device. the ?symbol? column of the electrical parameter a nd timings tables may contain an additional column containing ?sr?, ?cc?, ?p?, ?c?, ?t? or ?d?. ? ?sr? identifies system requireme nts?conditions that must be pr ovided to ensure normal device operation. an example is the input voltage of a voltage regulator. ? ?cc? identifies specifications that define norm al device operation. where available, the letters ?p?, ?c?, ?t? or ?d? replace the letter ?cc? and apply to these c ontroller characteristics. they specify how each characte ristic is guaranteed. ? p: parameter is guaranteed by production testing of each individual device. ? c: parameter is guaranteed by design charac terization. measurements are taken from a statistically relevant sample size across process variations. ? t: parameter is guaranteed by design characteri zation on a small sample size from typical devices under typical conditions unless otherwise noted. all valu es are shown in the typical (?typ?) column are within this category. ? d: parameters are derived mainly from simulations. 3.2 absolute maximum ratings table 11. absolute maximum ratings 1 no. symbol parameter conditions min max 2 unit 1v dd_hv_pmu sr voltage regulator supply voltage ??0.35.5 3 v 2v ss_hv_pmu sr voltage regulator supply ground ??0.10.1v 3v dd_hv_io sr input/output supply voltage ??0.33.6 4,5 v 4v ss_hv_io sr input/output supply ground ??0.10.1v 5v dd_hv_fla sr flash supply voltage ??0.33.6 4,5 v 6v ss_hv_fla sr flash supply ground ??0.10.1v 7v dd_hv_osc sr crystal oscillator amplifier supply voltage ??0.33.6 4,5 v 8v ss_hv_osc sr crystal oscillator amplifier supply ground ??0.10.1v 9v dd_hv_pdi sr pdi interface supply voltage ??0.33.6 4,5 v 10 v ss_hv_pdi sr pdi interface supply ground ??0.10.1v 11 v dd_hv_dram sr dram interface supply voltage ??0.33.6 4,5 v 12 v ss_hv_dram sr dram interface supply ground ??0.10.1v 13 v dd_hv_adrx 6 sr adc x high reference voltage ??0.36.0v 14 v ss_hv_adrx sr adc x low reference voltage ??0.10.1v
electrical characteristics mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 71 3.3 recommended operating conditions 15 v dd_hv_adv sr adc supply voltage ??0.33.6 4,5 v 16 v ss_hv_adv sr adc supply ground ??0.10.1v 17 v dd_lv_cor sr core supply voltage digital logic ??0.31.32 7 v 18 v ss_lv_cor sr core supply voltage ground digital logic ??0.10.1v 19 v dd_lv_pll sr pll supply voltage ??0.31.4 v 20 v ss_lv_pll sr pll reference voltage ??0.10.1v 21 tv dd sr slope characteristics on all v dd during power up ??25mv/s 22 v in sr voltage on any pin with respect to its supply rail v dd_hv_xxx relative to v dd_hv_xxx ?0.3 v dd_hv_xxx +0.3 8 v 23 i injpad sr injected input current on any pin during overload condition (incl. analog pins tbd) ? ?10 10 ma 24 i injpada sr injected input current on any analog pin during overload condition ? ?3 3 ma 25 i injsum sr absolute sum of all injected input currents during overload condition ? ?50 50 ma 26 t stg sr storage temperature ? ?55 150 c 27 t sdr sr maximum solder temperature 9 pb-free package snpb package ? ? ? 260 245 c 28 msl sr moisture sensitivity level 10 ??3? notes: 1 functional operating conditions are given in the dc electric al characteristics. absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. stress beyond the listed maxima may affect device reliability or cause permanent damage to the device. 2 absolute maximum voltages are currently maximum burn-in vo ltages. absolute maximum specifications for device stress have not yet been determined. 3 tbd v for 10 hours cumulative ti me, 5.0 v + 10% for time remaining. 4 5.3 v for 10 hours cumulative over lifetime of device, 3.63 v for time remaining. 5 voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance. 6 all v dd_hv_adrx rails must be operated at the same supply voltage. 7 2.0 v for 10 hours cumulative time, 1.2 v + 10% for time remaining. 8 only when v dd_hv_xxx < 5.2 v. 9 solder profile per cdf-aec-q100. 10 moisture sensitivity per jedec test method a112. table 12. recommended operating conditions 1 no. symbol parameter conditions min max unit 1v dd_hv_pmu sr voltage regulator supply voltage ?3.05.5v table 11. absolute maximum ratings 1 (continued) no. symbol parameter conditions min max 2 unit
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice electrical characteristics freescale semiconductor 72 2v ss_hv_pmu sr voltage regulator supply ground ?00v 3v dd_hv_io sr input/output supply voltage ?3.03.6v 4v ss_hv_io sr input/output supply ground ?00v 5v dd_hv_fla sr flash supply voltage ?3.03.6v 6v ss_hv_fla sr flash supply ground ?00v 7v dd_hv_osc sr crystal oscillator amplifier supply voltage ?3.03.6v 8v ss_hv_osc sr crystal oscillator amplifier supply ground ?00v 9v dd_hv_pdi sr pdi interface supply voltage ? 1.62 3.6 v 10 v ss_hv_pdi sr pdi interface supply ground ?00v 11 v dd_hv_dram sr dram interface supply voltage ? 1.62 3.6 v 12 v ss_hv_dram sr dram interface supply ground ?00v 13 v dd_hv_adrx sr adc x high reference voltage ?3.03.6v alternate input voltage 4.5 5.5 14 v ss_hv_adrx sr adc x low reference voltage ?00v 15 v dd_hv_adv sr adc supply voltage ?3.03.6v 16 v ss_hv_adv sr adc supply ground ?00v 17 v dd_lv_cor sr core supply voltage digital logic 2 external vreg mode 1.14 1.32 v 17a cc internal vreg mode 1.14 1.32 v 18 v ss_lv_cor sr core supply voltage ground digital logic ?00v 19 v dd_lv_pll sr pll supply voltage 2 external vreg mode 1.14 1.32 v 19a cc internal vreg mode 1.14 1.32 v 20 v ss_lv_pll sr pll reference voltage ?00v 21 t a sr ambient temperature under bias 3 257 mapbga ?40 105 4 c 473 mapbga ?40 125 c 22 t j sr junction temperature under bias 257 mapbga ?40 150 c 473 mapbga ?40 150 notes: 1 these specifications are design targets and are subject to change per device characterization. 2 the jitter specifications for both plls holds true only up to 50 mv noise (peak to peak) on v dd_lv_cor and v dd_lv_pll . 3 see ta bl e 1 for available frequency and package options. 4 preliminary data. table 12. recommended operating conditions 1 (continued) no. symbol parameter conditions min max unit
electrical characteristics mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 73 3.4 thermal characteristics 3.4.1 general notes for specificatio ns at maximum ju nction temperature an estimation of the chip junction temperature, t j , can be obtained from equation 1 : t j =t a +(r ? ja p d ) eqn. 1 where: t a = ambient temperature for the package ( o c) r ? ja = junction to ambient thermal resistance ( o c/w) p d = power dissipation in the package (w) the junction to ambient thermal resistance is an i ndustry standard value that provides a quick and easy estimation of thermal performance. unfortunately, there are two valu es in common usage: the value determined on a single layer board and the value obtained on a board with two planes. for packages such as the pbga, these values can be different by a factor of two. which value is cl oser to the application depends on the power dissipated by other components on the board. the value obtained on a single layer table 13. thermal characteristics for package options 1 notes: 1 thermal characteristics are targets based on simulation th at are subject to change per device characterization. no. symbol parameter conditions value unit bga 257 bga 473 1r ? ja cc thermal resistance junction-to-ambient natural convection 2 2 junction-to-ambient thermal resistance determined per jedec jesd51-3 and jesd51-6. thermal test board meets jedec specification for this package. single layer board ? 1s ? 40 ? 34 c/w 2r ? ja cc thermal resistance junction-to-ambient natural convection 2 four layer board ? 2s2p ? 22 ? 20 c/w 3r ? jma cc thermal resistance junction-to-moving-air ambient 2 @ 200 ft./min., single layer board ? 1s ? 32 ? 26 c/w 4r ? jma cc thermal resistance junction-to-moving-air ambient 2 @ 200 ft./min., four layer board ? 2s2p ? 18 ? 17 c/w 5r ? jb cc thermal resistance junction-to-board 3 3 junction-to-board thermal resistanc e determined per jedec jesd51-8. thermal test board meets jedec specification for the specified package. ? ? 10 ? 10 c/w 6r ? jc cc thermal resistance junction-to-case 4 4 junction-to-case at the top of the package determi ned using mil-std 883 method 1012.1. the cold plate temperature is used for the case temperature. reported va lue includes the thermal resistance of the interface layer. ? ? 6 ? 6 c/w 7 ? jt cc junction-to-package-top natural convection 5 5 thermal characterization parameter indicating the te mperature difference between the package top and the junction temperature per jedec jesd51-2. when greek le tters are not available, the thermal characterization parameter is written as psi-jt. ? ? 2 ? 2c/w
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice electrical characteristics freescale semiconductor 74 board is appropriate for the tightly packed printed circuit board. the va lue obtained on the board with the internal planes is usually appropria te if the board has low power diss ipation and the components are well separated. when a heat sink is us ed, the thermal resistan ce is expressed in equation 2 as the sum of a junction to case thermal resistance and a case to ambient thermal resistance: r ? ja =r ? jc + r ? ca eqn. 2 where: r ? ja = junction to ambient thermal resistance (c/w) r ? jc = junction to case thermal resistance (c/w) r ? ca = case to ambient thermal resistance (c/w) r ? jc is device related and cannot be influenced by the user. the user c ontrols the thermal environment to change the case to ambient thermal resistance, r ? ca . for instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounti ng arrangement on printed circuit board, or change the thermal dissipation on th e printed circuit board surrounding the device. to determine the junction temperatur e of the device in the application when heat sinks are not used, the thermal characterization parameter ( ? jt ) can be used to determine th e junction temperature with a measurement of the temperature at the top center of the package case using equation 3 : t j =t t +( ? jt p d ) eqn. 3 where: t t = thermocouple temperature on top of the package (c) ? jt = thermal characterizat ion parameter (c/w) p d = power dissipation in the package (w) the thermal characterization parame ter is measured per jesd51-2 spec ification using a 40 gauge type t thermocouple epoxied to the top center of the pack age case. the thermocouple should be positioned so that the thermocouple junction rests on the packag e. a small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from th e junction. the thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. see [6] to [10] in section 6, refere nce documents, for more information. 3.5 electromagnetic interference (emi) characteristics 3.5.1 test setup electromagnetic emission tests are performed by tem cell [2] and via direct coupling [3] (150 ohm) measurements. electromagnetic immunity are measured by dpi [4] .
electrical characteristics mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 75 see section 6, reference documents, for more information. 3.5.2 test parameters the following test parameters shall be used: in case of only narrow band disturban ces the maximum of the results will not change. in case of broadband signals the emission has to be below the limits. 3.6 electrostatic discharge (esd) characteristics electrostatic discharges (a positive th en a negative pulse sepa rated by 1 second) are a pplied to the pins of each sample according to each pin combination. the sa mple size depends on the number of supply pins in the device (3 parts ( n + 1) supply pin). this test conforms to the aec-q100-002/-003/-011 standard. 3.7 static latch-up (lu) two complementary static tests are required on six parts to assess the latch-up performance: ? a supply over voltage is applied to each power supply pin. ? a current injection is applied to eac h input, output and configurable i/o pin. these tests are compliant with the eia/jesd 78 ic latch-up standard. table 14. emc test parameters method frequency range receiver bw step size 150 ohm 1 mhz to 1000 mhz 1 mhz 500 khz tem table 15. esd ratings 1, 2 notes: 1 all esd testing is in conformity with cdf-aec-q100 st ress test qualification for automotive grade integrated circuits. 2 a device will be defined as a failure if after exposure to esd pulses the device no longer meets the device specification requirements. complete dc parametric and functional testing shall be performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. no. symbol parameter conditions class max value 3 3 data based on characterization resu lts, not tested in production. unit 1v esd(hbm) sr electrostatic discharge (human body model) t a =25c conforming to aec-q100-002 h1c 2000 v 2v esd(mm) sr electrostatic discharge (machine model) t a =25c conforming to aec-q100-003 m2 200 v 3v esd(cdm) sr electrostatic discharge (charged device model) t a =25c conforming to aec-q100-011 c3a 750 (corners) v 500
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice electrical characteristics freescale semiconductor 76 3.8 power management controller (pmc) electrical characteristics 3.8.1 pmc electrical specifications this section contains electrical characteristics for the pmc. table 16. latch-up results no. symbol parameter conditions class 1lucc static latch-up class t a = 125 c conforming to jesd 78 ii level a table 17. pmc electrical specifications no. symbol parameter min typ max unit 2 v dd_lv_cor cc nominal v rc regulated 1.2 v output v dd_hv_pmu ?1.28?v 3 porc cc por rising v dd 1.2 v ? por v dd variation ? por 1.2 v hysteresis ? porc ? 30% ? 0.7 porc 75 ? porc + 30% ? v v mv 4lvdc cc nominal lvd 1.2 v ? lvd 1.2 v at reset (lvdcr) ? lvd 1.2 v variation at reset ? lvd 1.2 v variation after reset ? lvd 1.2 v hysteresis ? ? lvdc ? 3.5% lvdc ? 3% 10 1.175 1 1.215 1 lvdc 1 lvdc 1 15 notes: 1 rising v dd . ? ? lvdc + 3.5% lvdc + 3% 20 v v v v mv 5 hvdc cc nominal hvd 1.2 v ? hvd 1.2 v at reset (hvdcr) ? hvd 1.2 v variation at reset ? hvd 1.2 v variation after reset ? hvd 1.2 v hysteresis ? ? hvdc ? 3.5% hvdc ? 3% 10 1.32 1 1.44 1 hvdc 1 hvdc 1 15 ? ? hvdc + 3.5% hvdc + 3% 20 v v v mv 6 vddstepc cc trimming step lvd 1.2 v, hvd 1.2 v, vrc 1.2 v ?5?mv 7 porreg cc por rising on v ddreg ? por v ddreg variation ? por v ddreg hysteresis ? porreg?30% ? 2.00 porreg 250 ? porreg +30% ? v v mv 8 lvdreg cc nominal rising lvd 3.3 v on v ddreg , v ddio , v ddflash , and v ddadc ? lvd 3.3 v variation at reset ? lvd 3.3 v variation after reset ? lvd 3.3 v hysteresis ? minimum slew rate ? maximum slew rate ? lvdreg ? 3.5% lvdreg ? 3% ? ? ? 2.865 lvdreg 1 lvdreg 1 30 50 25 ? lvdreg +3.5% lvdreg +3% ? ? ? v v v mv mv/ms mv/s 9 lvdstepreg cc trimming step lvd 3.3 v ?30?mv
electrical characteristics mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 77 3.8.2 pmc board schematic and components figure 7 shows a sample application for the pmc. figure 7. pmu mandatory external components table 18. vrc smps recommended external devices reference designator part description part type nominal description ca ? capacitor 20 f, 20 v filter capacitor cb ? capacitor 0.1 f, 20 v filter capacitor cd ? capacitor 20 f, 20 v supply decoupling cap, esr < 50 m ? , as close to p-mos source as possible ce ? capacitor 0.1 f, 16 v ceramic cl ? capacitor 20 f, 16 v buck capacitor, total esr < 100 m ? , as close to the coil as possible d ss8p3l schottky ? vishay low vf schottky diode l ? inductor 4 h, 1.5 a buck shielded coil low esr q sud50p04/sqd50p04 pmos 2 a, 40 v vishay low threshold p-mos, v th < 2.5 v, rdson@4.5 v < 20 m ? , cg <5nf r ? resistor 50?100 k ? pull up for power p-mos gate vdd_hv_pmu vss_hv_pmu vreg_ctrl vdd_lv_cor vss_lv_cor ca cb cd ce cl l r d q
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice electrical characteristics freescale semiconductor 78 3.9 supply current characteristics 3.10 temperature sensor electrical characteristics table 19. current consumption characteristics 1 notes: 1 applies to t j = ?40 c to 150 c. no. symbol parameter conditions min typ max unit 1i dd_lv cc maximum run i dd (incl. digital core logic and analog block of the lv rail) v dd_lv = 1.36 v, f core = 180 mhz, 1:2 mode, dpm, both cores executing emc test code, internal vreg mode, all caches enabled, code execution of core 0 from code flash 0, code execution of core 1 from code flash 1, fmpll_1 active at 120 mhz. ? 600 900 ma 2i dd_lv_pll cc maximum run i dd for each pll 2 2 total current on i dd_lv_pll needs to be multiplied with the number of active plls. v dd_lv_pll = 1.36 v, f vco running at maximum frequency. ?1.5 2 ma 3i dd_hv_fla cc maximum run i dd flash v dd_hv_fla = 3.6 v, dpm, both cores executing emc test code, code execution of core 0 from code flash 0, code execution of core 1 from code flash 1. ?2030ma 4i dd_hv_osc cc maximum run i dd osc f osc 4 mhz to 40 mhz, v dd_hv_osc 3.6 v ?1 3ma 5i dd_hv_adv cc maximum run i dd for each adc 3 3 total current on i dd_hv_adv needs to be multiplied with the number of active adcs. v dd_hv_adv =3.6v ?2 4ma 6i dd_hv_adr02 4 4 257 mapbga only. cc maximum reference i dd 5 5 total current on i dd_hv_adrxx is the sum of both references if both adcs are powered on. adc0 powered on 6 6 adc0 includes 0.7 ma dissipation for the temperature sensor (tsens). ?? 2ma adc2 powered on ??1.2ma 7i dd_hv_adr13 4 cc maximum reference i dd 5 adc1 powered on ??1.2ma adc3 powered on ??1.2ma 8i dd_hv_adr0 7 7 473 mapbga only. cc maximum reference i dd adc0 powered on 6 ?? 2ma 9i dd_hv_adr1 7 cc maximum reference i dd adc1 powered on ??1.2ma 10 i dd_hv_adr23 7 cc maximum reference i dd 5 adc2 powered on ??1.2ma adc3 powered on ??1.2ma table 20. temperature sensor electrical characteristics symbol parameter conditions min max unit 1?p accuracy t j = ?40 c to t a = 125 c ?10 10 c
electrical characteristics mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 79 3.11 main oscillator electrical characteristics the mpc5675k provides an os cillator/resonator driver. 3.12 fmpll electrical characteristics 2t s d minimum sampling period ? 4 ? s table 21. main oscillator electrical characteristics no. symbol parameter conditions 1 notes: 1 v dd = 3.0 v to 3.6 v, t j = ?40 to 150 c, unless otherwise specified. value unit min typ max 1f xoschs sr oscillator frequency ? 4.0 ? 40.0 mhz 2t xoschssu cc oscillator start-up time f osc = 4 mhz to 40 mhz ?tbdtbds 3v ih sr input high level cmos schmitt trigger oscillator bypass mode 0.65 v dd ?v dd +0.4 v 4v il sr input low level cmos schmitt trigger oscillator bypass mode ?0.4 ? 0.35 v dd v table 22. fmpll electrical characteristics symbol parameter conditions min typ max unit f ref_crystal f ref_ext d fmpll reference frequency range 1 crystal reference tbd ? tbd mhz f pll_in d phase detector input frequency range (after pre-divider) ? tbd ? tbd mhz f fmpllout d clock frequency range in normal mode see chapter 30, ?frequency-modulated phase-locked loop (fmpll),? in the mpc5675k reference manual (mpc5675krm) for more details on pll configuration. 16 ? 256 mhz f free p free running frequency measured using clock division (typically ? 16) tbd ? tbd mhz f sys d on-chip fmpll frequency 2 ? tbd ? tbd mhz t cyc d system clock period ? ? ? 1 / f sys ns f lorl f lorh d loss of reference frequency window 2 lower limit tbd ? tbd mhz upper limit tbd ? tbd f scm d self-clocked mode frequency 3,4 ? tbd ? tbd mhz table 20. temperature sensor electrical characteristics (continued) symbol parameter conditions min max unit
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice electrical characteristics freescale semiconductor 80 t lock p lock time stable oscillator (f pllin = 4 mhz), stable v dd ? ? 200 s t lpll d fmpll lock time 5, 6 ??? tbd ? s t dc d duty cycle of reference ?40?60% c jitter t clkout period jitter 7,8,9,10 peak-to-peak (clock edge to clock edge), f sys maximum tbd ? tbd ps long-term jitter (avg. over 2 ms interval), f sys maximum tbd ? tbd ns ? t pkjit t single period jitter (peak to peak) phi @ 16 mhz, input clock @ 4 mhz ?? 500 ps ? t ltjit t long term jitter phi @ 16 mhz, input clock @ 4 mhz ?? 6 ns f lck d frequency lock range ? tbd ? tbd % f sys f ul d frequency un-lock range ? tbd ? tbd % f sys f cs f ds d modulation depth center spread tbd ? tbd % f sys down spread tbd ? tbd f mod d modulation frequency 11 ? tbd ? tbd khz notes: 1 considering operation with fmpll not bypassed. 2 ?loss of reference frequency? window is the reference fr equency range outside of which the fmpll is in self clocked mode. 3 self clocked mode frequency is the frequency that the fm pll operates at when the reference frequency falls outside the f lor window. 4 f vco is the frequency at the output of the vco; its range is 256?512 mhz. f scm is the self-clocked mode frequency (free running frequency); its range is 20?150 mhz. f sys =f vco ? odf 5 this value is determined by the crystal manufacturer and board design. for 4 mhz to 20 mhz crystals specified for this fmpll, load capacitors should not exceed these limits. 6 this specification applies to the period required for th e fmpll to relock after changing the mfd frequency control bits in the synthesizer control register (syncr). 7 this value is determined by the cr ystal manufacturer and board design. 8 jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f sys . measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. noise injected into the fmpll circuitry via v ddpll and v sspll and variation in crystal oscillator frequency increase the c jitter percentage for a given interval. 9 proper pc board layout procedures must be followed to achieve specifications. 10 values are with frequency modulation disabled. if frequ ency modulation is enabled, jitter is the sum of c jitter and either f cs or f ds (depending on whether center spread or down spread modulation is enabled). 11 modulation depth is attenuated from depth setting when operating at modulation frequencies above 50 khz. table 22. fmpll electrical characteristics (continued) symbol parameter conditions min typ max unit
electrical characteristics mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 81 3.13 16 mhz rc oscillator electrical characteristics 3.14 adc electrical characteristics the mpc5675k provides a 12-bit successive a pproximation register (s ar) analog-to-digital converter. figure 8. adc characteristics and error definitions table 23. rc oscillator el ectrical characteristics no. symbol parameter conditions min typ max unit 1f rc cc rc oscillator frequency 27 c, 1.2 v trimmed ?16?mhz 2 ? rcmvar cc frequency spread: the variation in output frequency from ptf 1 across temperature and supply voltage range notes: 1 ptf = post trimming frequency: the frequency of the out put clock after trimming at typical supply voltage and temperature. ???5% 3 ? irctrim cc internal rc oscillator trimming step t a = 25 c ? 1.6 ? % (2) (1) (3 ) (4) (5) offset error ose offset error ose gain error ge 1 lsb (ideal) v in(a) (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) differential non-linearity error (dnl) (4) integral non-linearity error (inl) (5) center of a step of the actual transfer curve code out 4095 4094 4093 4092 4091 4090 5 4 3 2 1 0 7 6 1 2 3 4 5 6 7 4089 40904091 4092 4093 4094 4095 1 lsb ideal =(vrefh-vrefl)/ 4096 = 3.3 v/ 4096 = 0.806 mv total unadjusted error tue = 6 lsb = 4.84 mv
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice electrical characteristics freescale semiconductor 82 3.14.1 input impedance and adc accuracy to preserve the accuracy of the a/d converter, it is necessary that analog input pins have low ac impedance. placing a capacitor with good high frequency character istics at the input pin of the device can be effective: the capacitor should be as large as possible, ideally infi nite. this capacito r contributes to attenuating the noise present on the i nput pin; further, it sources charge during th e sampling phase, when the analog signal source is a high-impedance source. a real filter can typi cally be obtained by using a series resistan ce with a capacitor on the input pin (simple rc filter). the rc filtering may be limited acco rding to the value of source impedance of the transducer or circuit supplying the anal og signal to be measured. th e filter at the input pins must be designed taking into account the dynamic characteristics of the i nput signal (bandwidth) and the equivalent input impedance of the adc itself. in fact a current sink contributor is represente d by the charge sharing effects with the sampling capacitance: c s being substantially a switched capacitance, with a frequency equal to the conversion rate of the adc, it can be seen as a re sistive path to ground. fo r instance, assuming a c onversion rate of 1 mhz, with c s equal to 3 pf, a resistance of 330 k ? is obtained (r eq =1 / (f c ? c s ), where f c represents the conversion rate at the considered channel). to mi nimize the error induced by the voltage partitioning between this resistance (sampled voltage on c s ) and the sum of r s +r f +r l +r sw +r ad , the external circuit must be designed to respect the equation 9 : eqn. 9 equation 9 generates a constraint for external network de sign, in particular on resistive path. internal switch resistances (r sw and r ad ) can be neglected with resp ect to external resistances. figure 10. input equivalent circuit v a r s r f r l r sw r ad +++ + r eq -------------------------------------------------------------------------- - ? 1 2 -- -lsb ? r s source impedance r f filter resistance c f filter capacitance r l current limiter resistance r sw1 channel selection switch impedance r ad sampling switch impedance c p pin capacitance (two contributions, c p1 and c p2 ) c s sampling capacitance c p1 r ad channel selection v a c s
electrical characteristics mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 83 a second aspect involving the capaci tance network shall be considered. assuming the three capacitances c f , c p1 , and c p2 are initially charged at the source voltage v a (please see the equivalent circuit in figure 10 ): a charge sharing phenomenon is installed when the sampling phase is started (a/d switch is closed). figure 11. transient behavior during sampling phase in particular two different transi ent periods can be distinguished: ? a first and quick charge transfer from the internal capacitance c p1 and c p2 to the sampling capacitance c s occurs (c s is supposed initially completely di scharged): considering a worst case (since the time constant in real ity would be faster) in which c p2 is reported in parallel to c p1 (call c p = c p1 + c p2 ), the two capacitances c p and c s are in series, and th e time constant is: eqn. 12 equation 12 can again be simplified considering only c s as an additional worst condition. in reality, the transient is faster, but the a/d converter circuitry has been designed to be robust also in the very worst case: the sampling time t s is always much longer than the internal time constant: eqn. 13 the charge of c p1 and c p2 is redistributed also on c s , determining a new value of the voltage v a1 on the capacitance according to equation 14 : eqn. 14 ? a second charge transfer involves also c f (that is typically bigger th an the on-chip capacitance) through the resistance r l : again considering the worst case in which c p2 and c s were in parallel to c p1 (since the time constant in reality w ould be faster), the time constant is: eqn. 15 in this case, the time constant depends on the ex ternal circuit: in part icular imposing that the transient is completed well before the end of sampling time t s , a constraints on r l sizing is obtained: v a v a1 v a2 t t s v cs voltage transient on c s ? v < ? 0.5 lsb ? 1 2 ? 1 < (r sw + r ad ) c s << t s ? 2 = r l (c s + c p1 + c p2 ) ? 1 r sw r ad + ?? = c p c s ? c p c s + --------------------- ? ? 1 r sw r ad + ?? ? c s t s ? ? ?? ? v a c p1 c p2 + ?? ? = ? 2 r l ? c s c p1 c p2 ++ ?? ?
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice electrical characteristics freescale semiconductor 84 eqn. 16 of course, r l shall be sized also according to the curr ent limitation constraints, in combination with r s (source impedance) and r f (filter resist ance). being c f definitively bigger than c p1 , c p2 and c s , then the final voltage v a2 (at the end of the charge transfer transient) will be much higher than v a1 . equation 17 must be respected (cha rge balance assuming now c s already charged at v a1 ): eqn. 17 the two transients above are not influenced by the voltage source that, due to the presence of the r f c f filter, is not able to provi de the extra charge to compensate the voltage drop on c s with respect to the ideal source v a ; the time constant r f c f of the filter is very high with respect to the sampling time (t s ). the filter is typically designed to act as anti-aliasing. figure 18. spectral representation of input signal calling f 0 the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, f f ), according to the nyquist theorem the conversion rate f c must be at least 2f 0 ; it means that the constant time of the filter is greater than or at leas t equal to twice the conversion period (t c ). again the conversion period t c is longer than the sampling time t s , which is just a portion of it, even when fixed channel continuous conversion mode is sele cted (fastest conversi on rate at a specific channel): in conclusion it is evident th at the time constant of the filter r f c f is definitively much higher than the sampling time t s , so the charge level on c s cannot be modified by the analog signal source during the time in which the sampling switch is closed. the considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage drop on c s ; from the two charge balance equati ons above, it is simple to derive equation 19 between the ideal and real sampled voltage on c s : eqn. 19 10 ? 2 ? 10 r l c s c p1 c p2 ++ ?? ? ? =t s ? v a2 c s c p1 c p2 c f +++ ?? ? v a c f ? v a1 +c p1 c p2 +c s + ?? ? = f 0 f analog source bandwidth (v a ) f 0 f sampled signal spectrum (f c = conversion rate) f c f anti-aliasing filter (f f = rc filter pole) f f 2 f 0 ?? f c (nyquist) f f ? f 0 (anti-aliasing filtering condition) t c ?? 2 r f c f (conversion rate vs. filter pole) noise v a v a2 ----------- - c p1 c p2 +c f + c p1 c p2 +c f c s ++ ------------------------------------------------------- - =
electrical characteristics mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 85 from this formula, in the worst case (when v a is maximum, that is for instance 5 v), assuming to accept a maximum error of half a count, a constraint is evident on c f value: eqn. 20 table 24. adc conversion characteristics no. symbol parameter conditions 1 notes: 1 v dd = 3.3 v, t j = ?40 to +150 c, unless otherwise specified and analog input voltage from v agnd to v aref . min typ max unit 1f ck sr adc clock frequency (depends on adc configuration) (the duty cycle depends on ad_ck 2 frequency) 2 ad_ck clock is always half of the adc module input clock defined via the auxiliary clock divider for the adc. ?3?60mhz 2f s sr sampling frequency ? ? ? 959 khz 3t adc_s d sample time 3 60 mhz 383 ? ? ns 4t adc_e p evaluation time 4 tbd 600 ? ? ns 5c s 5 d adc input sampling capacitance ? ? ? 7.32 pf 6c p1 5 d adc input pin capacitance 1 ???2.5 pf 7c p2 5 d adc input pin capacitance 2 ???tbd pf 8r sw1 5 d channel selection switch resistance v ref range=4.5to5.5v ? ? 1.0 k ? 9v ref range=3.0to3.6v ? ? 1.2 k ? 10 r ad 5 d sample switching resistance ? ? ? 825 ? 11 i inj t current injection current injection on one adc input channel, different from the converted one. other parameters stay within specified limits as long as the adc supply stays within its specified limits due to the current injection. ?3 ? 3 ma 12 inl p integral non linearity ??3?3lsb 13 dnl p differential non linearity 6 ??1.0?1.0lsb 14 ofs t offset error ??4? 4lsb 15 gne t gain error ??4? 4lsb 16 tue p total unadjusted error ??6?6lsb 17 tue t total unadjusted error with current injection ? tbd ? tbd lsb 18 snr t signal-to-noise ratio ?69??db 19 thd t total harmonic distortion ?tbd??db 20 sinad t signal-to-noise and distortion ?65??db 21 enob t effective number of bits ?10.5??bits c f 8192 c s ? ?
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice electrical characteristics freescale semiconductor 86 3 during the sample time the input capacitance c s can be charged/discharged by the external source. the internal resistance of the analog source must allow the capa citance to reach its final voltage level within t adc_s . after the end of the sample time t adc_s , changes of the analog input voltage have no ef fect on the conversion result. values for the sample clock t adc_s depend on programming. 4 this parameter does not include the sample time t adc_s , but only the time for determining the digital result and the time to load the result register with the conversion result. 5 see figure 10 . 6 no missing codes.
electrical characteristics mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 87 3.15 flash memory electrical characteristics 3.15.1 program/erase characteristics table 25 shows the code flash memory program and erase characteristics. table 26 shows the data flash memory program and erase characteristics. table 25. code flash program and erase electrical specifications no. symbol parameter min typ 1 notes: 1 typical program and erase times assume nominal supply values and operation at 25 c. all times are subject to change pending device characterization. initial max 2 2 initial max program and erase times provide guidance for time-out limits used in the factory and apply for < 100 program/erase cycles, nominal supp ly values and operation at t j = 25 c. these values are verified at production test. lifetime max 3 3 lifetime max program and erase times apply across the voltage, temperature, and cycling range of product life. these values are characterized, but not tested. unit 1t dwprogram cc double word (64 bits) program time 4 4 actual hardware programming times. this does not include software overhead. ? 18 50 500 s 3t 16kpperase cc 16 kb block pre-program and erase time ? 200 500 5000 ms 4t 32kpperase cc 32 kb block pre-program and erase time ? 300 600 5000 ms 5t 64kpperase cc 64 kb block pre-program and erase time ? 400 900 5000 ms 6t 128kpperase cc 128 kb block pre-program and erase time ? 600 1300 7500 ms table 26. data flash program and erase electrical specifications no. symbol parameter min typ 1 notes: 1 typical program and erase times assume nominal supply values and operation at 25 c. all times are subject to change pending device characterization. initial max 2 2 initial max program and erase times provide guidance for time-out limits used in the factory and apply for < 100 program/erase cycles, nominal supp ly values and operation at t j = 25 c. these values are verified at production test. lifetime max 3 3 lifetime max program and erase times apply across the voltage, temperature, and cycling range of product life. these values are characterized, but not tested. unit 1t dwprogram cc double word (64 bits) program time 4 4 actual hardware programming times. this does not include software overhead. ? 30 70 300 s 3t 16kpperase cc 16 kb block pre-program and erase time ? 700 800 1500 ms
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice electrical characteristics freescale semiconductor 88 3.15.2 read access timing 3.15.3 write access timing table 27. flash module life no. symbol parameter condition value unit min typ 1 notes: 1 typical endurance is evaluated at 25 o c. product qualification is performed to the minimum specification. for additional information on the freescale definition of typica l endurance, please refer to engineering bulletin eb619, typical endurance for nonvolatile memory . max 1a p/e cc number of program/erase cycles per block for over the operating temperature range (t j ) 16 kb blocks 100,000 ? ? cycles 1b 32 kb and 64 kb blocks 10,000 100,000 ? cycles 1c 128 kb blocks 1,000 100,000 ? cycles 2 retention cc minimum data retention at 85 c average ambient temperature 2 2 ambient temperature averaged over duration of application, not to exceed product operating temperature range. blocks with 0?1,000 p/e cycles 20 ? ? years blocks with 1,001?10,000 p/e cycles 10 ? ? years blocks with 10,001?100,000 p/e cycles 5??years table 28. code flash read access timing no. symbol parameter condition value unit max 2f read cc maximum frequency for flash reading (system clock frequency sys_clk) 4 wait states 90 mhz 3 3 wait states 60 mhz table 29. data flash read access timing no. symbol parameter condition value unit max 2f read cc maximum frequency for flash reading (system clock frequency sys_clk) 12 wait states 90 mhz 3 8 wait states 60 mhz table 30. code flash write access timing no. symbol parameter condition value unit max 2f write cc maximum frequency for flash writing (system clock frequency sys_clk) tbd 90 mhz 3 tbd 60 mhz
electrical characteristics mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 89 3.16 sram memory electrical characteristics 3.16.1 read access timing 3.16.2 write access timing 3.17 gp pads specifications this section specifies the electrical characteristics of the gp pads . please refer to the tables in section 2.2, pin descriptions, for a cross reference between package pins and pad types. 3.17.1 gp pads dc specifications table 36 gives the dc electrical ch aracteristics at 3.3 v (3.0 v < v dd_hv_io < 3.6 v). table 31. data flash write access timing no. symbol parameter condition value unit max 2f write cc maximum frequency for flash writing (system clock frequency sys_clk) tbd 90 mhz 3 tbd 60 mhz table 32. system sram memory read access timing no. symbol parameter condition value unit max 2s read cc maximum frequency for system sram reading (system clock frequency sys_clk) 1 wait state 90 mhz 3 1 wait state 60 mhz table 33. system sram memory write access timing no. symbol parameter condition value unit max 2s write cc maximum frequency for system sram writing (system clock frequency sys_clk) tbd 90 mhz 3 tbd 60 mhz
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice electrical characteristics freescale semiconductor 90 table 34. gp pads dc el ectrical characteristics 1,2 notes: 1 these specifications are design targets and subject to change per device characterization. 2 the values provided in this table are not applicable for pdi and ebi/dram interface. no. symbol parameter conditions min max unit 1v il sr low level input voltage ? ?0.1 3 3 ?sr? parameter values must not exceed the absolute maximum ratings shown in ta b l e 1 1 . 0.35 v dd_hv_io v 2v ih sr high level input voltage ?0.65v dd_hv_io v dd_hv_io +0.1 3 v 3v hys cc schmitt trigger hysteresis ?0.1v dd_hv_io ?v 4v ol_s cc slow, low level output voltage i ol =1.5ma ? 0.5 v 5v oh_s cc slow, high level output voltage i oh =?1.5ma v dd_hv_io ?0.8 ? v 6v ol_m cc medium, low level output voltage i ol =2ma ? 0.5 v 7v oh_m cc medium, high level output voltage i oh =?2ma v dd_hv_io ?0.8 ? v 8v ol_f cc fast, high level output voltage i ol =11ma ? 0.5 v 9v oh_f cc fast, high level output voltage i oh =?11ma v dd_hv_io ?0.8 ? v 10 v ol_sym cc symmetric, high level output voltage i ol =5ma ? 0.5 v 11 v oh_sym cc symmetric, high level output voltage i oh =?5ma v dd_hv_io ?0.8 ? v 12 i pu cc equivalent pull-up current v in =v il ?130 ? a v in =v ih ? ?10 13 i pd cc equivalent pull-down current v in =v il 10 ? a v in =v ih ? 130 14 i il cc input leakage current (all bidirectional ports) t a = ?40 to 125 c ?1a 15 i il cc input leakage current (all adc input-only ports) t a = ?40 to 125 c ?0.5a 16 v ilr sr reset , low level input voltage ? ?0.4 3 0.35 v dd_hv_io v 17 v ihr sr reset , high level input voltage ?0.65v dd_hv_io v dd_hv_io +0.4 3 v 18 v hysr cc reset , schmitt trigger hysteresis ?0.1v dd_hv_io ?v 19 v olr cc reset , low level output voltage i ol =2ma ? 0.5 v 20 i pd cc reset , equivalent pull-down current v in =v il 10 ? a v in =v ih ? 130
electrical characteristics mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 91 3.17.2 gp pads ac specifications 3.18 pdi pads specifications this section specifies the electric al characteristics of the pdi pads . please refer to the tables in section 2.2, pin descriptions, for a cross reference between package pins and pad types. pdi pads feature list: ? direction ? input ? output ? bidirectional ? driver ? push/pull/open drain ? configurable four drive strengths on fast driver pads table 35. gp pads ac electrical characteristics 1 notes: 1 the values provided in this table are not applicable for pdi and ebi/dram interface. no. pad tswitchon 1 (ns) rise/fall 2 (ns) 2 slope at rising/falling edge. frequency (mhz) current slew 3 (ma/ns) 3 data based on characterization resu lts, not tested in production. load drive (pf) min typ max min typ max min typ max min typ max 1 slow 3 ? 40 4 ? 40 ? ? 4 0.01 ? 2 25 3?406?50??20.01?2 50 3 ? 40 10 ? 75 ? ? 2 0.01 ? 2 100 3 ? 40 14 ? 100 ? ? 2 0.01 ? 2 200 2 medium 1 ? 15 2 ? 12 ? ? 40 2.5 ? 7 25 1 ? 15 4 ? 25 ? ? 20 2.5 ? 7 50 1 ? 15 8 ? 40 ? ? 13 2.5 ? 7 100 1 ? 15 14 ? 70 ? ? 7 2.5 ? 7 200 3fast 1?61?4??723?4025 1?61.5?7??557?40 50 1?6 3?12??407?40 100 1?6 5?18??257?40 200 4symmetric1?8 1?5??503?25 25 5 pull up/down (3.6 v max) ?????7500?????? 50
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice electrical characteristics freescale semiconductor 92 ? configurable no slew-r ate, slow slew-rate, and fast slew-rate on slow, medium, and slr driver pads ? vdd_hv_pdi note: all pads ar e not 5 v tolerant. pads are not capable of driving to or from voltages above their respective vdd_ hv_pdi. in other words, you cannot connect a 3.3v external device to a pad supplied with 2.5 v. if a pad must be connected to a 3.3v device, its local vdd_hv_pdi must be 3.3 v. injection current is then handled by the intrinsic diodes from the pad transistors and by the esd diodes. ? vdd_hv_pdi range ? 1.8 v nominal ? 2.5 v nominal ? 3.3 v nominal ? receiver ? selectable hysteresis input buffer. ? cmos input buffer the electrical data provided in section 3.18, pdi pads specifications, applies to the pads listed in table 36 . 3.18.1 pdi pads electr ical specifications (v dd_hv_pdi = 3.3 v) table 36. pdi i/o pads no. name volt. used for notes 1 pdi fast 1.62 v-3.6 v i/o enhanced operating voltage range fast slew-rate output with four selectable slew-rates. contains an input buffer and weak pullup/pulldown. 2pdi medium 1.62 v-3.6 v i/o enhanced operating voltage range medium slew-rate output with four selectable slew-rates. contains an input buffer and weak pullup/pulldown. table 37. pdi pads dc electrical characteristics (v dd_hv_pdi = 3.3 v) no. symbol parameter min max unit 1v dd_hv_pdi sr i/o supply voltage 3.0 3.6 v 2v ih_c cc cmos input buffer high voltage (hysteresis enabled) 0.65 v dd_hv_pdi v dd_hv_pdi +0.3 v 3v ih_c cc cmos input buffer high voltage (hysteresis disabled) 0.51 v dd_hv_pdi v dd_hv_pdi +0.3 v 4v il_c cc cmos input buffer low voltage (hysteresis enabled) v ss ? 0.3 0.35 v dd_hv_pdi v 5v il_c cc cmos input buffer low voltage (hysteresis disabled) v ss ? 0.3 0.42 v dd_hv_pdi v 6v hys_c cc cmos input buffer hysteresis 0.1 v dd_hv_pdi v 7i act_s cc selectable weak pullup/pulldown current 3 25 150 a 9v oh cc output high voltage 0.8 v dd_hv_pdi ?v 10 v ol cc output low voltage ?0.2v dd_hv_pdi v
electrical characteristics mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 93 3.18.2 pdi pads electr ical specifications (v dd_hv_pdi = 2.5 v) table 38. drive current, v dd_hv_pdi = 3.3 v ( 10%) pad drive mode minimum i oh (ma) 1 notes: 1 i oh is defined as the current sourced by the pad to drive the output to v oh . minimum i ol (ma) 2 2 i ol is defined as the current sunk by the pad to drive the output to v ol . pdi fast all 84.4 137 pdi medium all 61.9 83.6 table 39. pdi pads ac electrical characteristics (v dd_hv_pdi = 3.3 v) no. name prop. delay (ns) l ? h/h ? l 1 notes: 1 l ? h signifies low-to-high propagation delay and h ? l signifies high-to-low propagation delay. rise/fall edge (ns) drive load (pf) drive/slew rate select minmaxminmax msb, lsb 1 pdi medium ? 4.0/4.5 ? 1.02/1.4 50 11 7.3/8.3 3.5/4.2 200 24/22 9.1/10.3 50 10 33/31 14/15 200 49/44 18/21 50 01 60/53 24/25 200 332/302 126/151 50 00 362/325 136/158 200 2 pdi fast ? 5/5 ? 1.1/1.1 50 11 8/8 2.6/2.6 200 8/8 2.4/2.4 50 10 12/12 5/5 200 13/13 5/5 50 01 19/19 8/8 200 40/40 16/16 50 00 50/50 21/21 200 table 40. pdi pads dc elec trical specifications (v dd_hv_pdi = 2.5 v) no. symbol parameter min max unit 1v dd_hv_pdi sr i/o supply voltage 2.3 2.7 v 2v ih_c cc cmos input buffer high voltage (hysteresis enabled) 0.65 v dd_hv_pdi v dd_hv_pdi +0.3 v
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice electrical characteristics freescale semiconductor 94 3v ih_c cc cmos input buffer high voltage (hysteresis disabled) 0.54 v dd_hv_pdi v dd_hv_pdi +0.3 v 4v il_c cc cmos input buffer low voltage (hysteresis enabled) vss ? 0.3 0.35 v dd_hv_pdi v 5v il_c cc cmos input buffer low voltage (hysteresis disabled) vss ? 0.3 0.42 v dd_hv_pdi v 6v hys_c cc cmos input buffer hysteresis 0.1 v dd_hv_pdi v 7i act_s cc selectable weak pullup/pulldown current 1 25 150 a 9v oh cc output high voltage 0.8 v dd_hv_pdi ?v 10 v ol cc output low voltage ?0.2v dd_hv_pdi v table 41. drive current @ v dd_hv_pdi = 2.5 v ( 10%) pad drive mode minimum i oh (ma) 1 notes: 1 i oh is defined as the current sourced by the pad to drive the output to v oh . minimum i ol (ma) 2 2 i ol is defined as the current sunk by the pad to drive the output to v ol . pdi pdi fast all 51.5 111 pdi medium all 52.6 78.1 table 42. pdi pads ac elec trical specifications (v dd_hv_pdi = 2.5 v) no. name prop. delay (ns) l ? h/h ? l 1 rise/fall edge (ns) drive load (pf) drive/slew rate select min max min max msb, lsb 1 pdi medium 0.8/0.7 -------- 1.1/1.08 4.5/4 1.3/1 ? 50 11 9/7 4.8/3.2 200 34/19 10.5/7.9 50 10 44/26 16.3/12 200 70/38 21/16 50 01 83/45 28/20 200 491/254 142/115 50 00 528/279 154/122 200 table 40. pdi pads dc electrical specifications (v dd_hv_pdi = 2.5 v) (continued) no. symbol parameter min max unit
electrical characteristics mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 95 3.18.3 pdi pads electr ical specifications (v dd_hv_pdi = 1.8 v) 2 pdi fast 0.8/0.7 -------- 1.1/1.08 5/5 1.5/1.5 ? 50 11 8.4/8.4 3.5/3.5 200 8.6/8.6 3/3 50 10 14/14 5.6/5.6 200 15.5/15.5 5.7/5.7 50 01 22/22 9.5/9.5 200 48/48 19/19 50 00 60/60 25/25 200 notes: 1 l ? h signifies low-to-high propagation delay and h ? l signifies high-to-low propagation delay. table 43. pdi pads dc elec trical specifications (v dd_hv_pdi = 1.8 v) no. symbol parameter min max unit 1v dd_hv_pdi sr i/o supply voltage 1.62 1.98 v 2v ih_c cc cmos input buffer high voltage (hysteresis enabled) 0.65 v dd_hv_pdi v dd_hv_pdi +0.3 v 3v ih_c cc cmos input buffer high voltage (hysteresis disabled) 0.58 v dd_hv_pdi v dd_hv_pdi +0.3 v 4v il_c cc cmos input buffer low voltage (hysteresis enabled) vss ? 0.3 0.35 v dd_hv_pdi v 5v il_c cc cmos input buffer low voltage (hysteresis disabled) vss ? 0.3 0.44 v dd_hv_pdi v 6v hys_c cc cmos input buffer hysteresis 0.1 v dd_hv_pdi ?v 7i act_s cc selectable weak pullup/pulldown current 1 25 150 a 9v oh cc output high voltage 0.8 v dd_hv_pdi ?v 10 v ol cc output low voltage ?0.2v dd_hv_pdi v table 44. drive current @ v dd_hv_pdi = 1.8 v ( 10%) pad drive mode minimum i oh (ma) 1 notes: 1 i oh is defined as the current sourced by the pad to drive the output to v oh . minimum i ol (ma) 2 2 i ol is defined as the current sunk by the pad to drive the output to v ol . pdi fast all 26.2 84.8 pdi medium all 19.2 52.1 table 42. pdi pads ac electrical specifications (v dd_hv_pdi = 2.5 v) (continued) no. name prop. delay (ns) l ? h/h ? l 1 rise/fall edge (ns) drive load (pf) drive/slew rate select min max min max msb, lsb
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice electrical characteristics freescale semiconductor 96 3.19 dram pad specifications this section specifies the electrica l characteristics of the dram pads . please refer to the tables in section 2.2, pin descriptions, for a cross reference betwee n package pins and pad types. dram pads feature list: ? driver ? configurable to support lpddr half stre ngth, lpddr full strength, ddr1, ddr2 half strength, ddr2 full strength, and sdr modes. ? vdd_hv_dram range of ? 1.8 v nominal ? 2.5 v nominal ? 3.3 v nominal ? receiver ? differential or pseudo-differential input buffer in all dram pads table 45. pdi pads ac elec trical specifications (v dd_hv_pdi = 1.8 v) no. name prop. delay (ns) l ? h/h ? l 1 notes: 1 l ? h signifies low-to-high propagation delay and h ? l signifies high-to-low propagation delay. rise/fall edge (ns) drive load (pf) drive/slew rate select min max min max msb, lsb 1 pdi medium ? 5.5/3.5 2/1 ? 50 11 12/5.5 7.2/2.3 200 49/17 13/6 50 10 60/23 21/9.2 200 102/32 26/12 50 01 119/39 35/16 200 722/216 172/85 50 00 772/237 191/90 200 2 pdi fast ? 10/10 2/2 ? 50 11 15/15 6.2/6.2 200 15/15 4.5/4.5 50 10 22/22 7.1/7.1 200 24/24 7.5/7.5 50 01 33/33 12/12 200 66/66 24/24 50 00 84/84 31/31 200
electrical characteristics mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 97 ? all inputs are tolerant up to their vdd_hv_dram absolute maximum rating ? data and strobe pads can be configured to support four signal termination options ? infinite/no termination ? 50 ohms ? 75 ohms ? 150 ohms the electrical data provided in section 3.19, dram pa d specifications, applies to the pads listed in table 46 . all three pad types can be configured to support sdr, ddr, ddr2 half and full strength, and lpddr half and full strength modes, according to table 47 . 3.19.1 dram pads electrical specifications (v dd_hv_dram = 3.3 v) table 46. dram pads name voltage used for notes 1 notes: 1 all pads can be configured to support lpddr hal f strength, lpddr full strength, ddr1, ddr2 half strength, ddr2 full strength, and sdr. dram acc 1.62 v?3.6 v i/o bidirectional ddr pad dram clk 1.62 v?3.6 v o output only differential clock driver pad dram dq 1.62 v?3.6 v i/o bidirect ional ddr pad with integrated odt table 47. mode config uration for dram pads configuration 1 notes: 1 configuration is selected in the co rresponding pcr registers of the siul. mode 000 1.8 v lpddr half strength 001 1.8 v lpddr full strength 010 1.8 v ddr2 half strength 011 2.5 v ddr 100 not supported 101 not supported 110 1.8 v ddr2 full strength 111 sdr table 48. dram pads dc elec trical specifications (v dd_hv_dram = 3.3 v) no. symbol parameter condition min max unit 1v dd_hv_dram sr i/o supply voltage ?3.0 3.6v 2 v dd_hv_dram_vref cc input reference voltage ?1.3 1.7v
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice electrical characteristics freescale semiconductor 98 3 v dd_hv_dram_vtt cc termination voltage 1 ?v dd_hv_dram_vref 0.05 v dd_hv_dram_vref +0.05 v 4v ih cc input high voltage ?v dd_hv_dram_vref + 0.20 ?v 5v il cc input low voltage ?v dd_hv_dram_vref 0.2 v 6v oh cc output high voltage odt enabled 2 v dd_hv_dram_vtt +0.8 ?v odt disabled 3 0.8 v dd_hv_dram ?v 7v ol cc output low voltage odt enabled 2 ?v dd_hv_dram_vtt 0.8 v odt disabled 3 ?v dd_hv_dram 0.2 v notes: 1 bga473: termination voltage can be supplied via package pins . bga257 termination voltage internally tied as the bga257 does not provide dram interface. disable odt 2 termination voltage is supplied by v dd_hv_dram_vtt . 3 tie v dd_hv_dram_vtt to v ss and disable odt table 49. output drive current @ v dde = 3.3 v ( 10%) no. pad name drive mode minimum i oh (ma) 1 minimum i ol (ma) 2 1 dram acc 111 ?16 16 2 dram dq 3 dram clk notes: 1 i oh is defined as the current sourced by the pad to drive the output to v oh . 2 i ol is defined as the current sunk by the pad to drive the output to v ol . table 50. dram pads ac elec trical specifications (v dd_hv_dram = 3.3 v) no. pad name prop. delay (ns) l ? h/h ? l 1 output slew rate rise/fall (v/ns) drive load (pf) drive/slew rate select minmaxminmax msb, lsb 1 dram acc 1.4/1.4 2.4/2.4 3.1/2.5 5.6/5.4 5 111 1.7/1.7 2.7/2.7 0.9/1.1 1.7/2.0 20 111 2 dram dq 1.4/1.4 2.4/2.4 3.1/2.5 5.6/5.4 5 111 1.7/1.7 2.7/2.7 0.9/1.1 1.7/2.0 20 111 3 dram clk 1.4/1.4 2.4/2.4 3.1/2.5 5.7/5.7 5 111 1.6/1.6 2.6/2.6 1.1/1.3 2.3/2.3 20 111 table 48. dram pads dc electrical specifications (v dd_hv_dram (continued) = 3.3 v) no. symbol parameter condition min max unit
electrical characteristics mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 99 3.19.2 dram pads electrical specification (v dd_hv_dram = 2.5 v) notes: 1 l ? h signifies low-to-high propagation delay and h ? l signifies high-to-low propagation delay. table 51. dram pads dc elec trical specifications (v dd_hv_dram = 2.5 v) no. symbol parameter condition min max unit 1v dd_hv_dram sr i/o supply voltage ?2.3 2.7v 2v dd_hv_dram_vref cc input reference voltage ? 0.49 v dd_hv_dram 0.51 v dd_hv_dram v 3v dd_hv_dram_vtt cc termination voltage 1 notes: 1 473 mapbga: termination voltage can be supplied via package pins. 257 mapbga termination voltage internally tied as the 257 mapbga does not pr ovide dram interface. disable odt ?v dd_hv_dram_vref - 0.04 v dd_hv_dram_vref +0.04 v 4v ih cc input high voltage ?v dd_hv_dram_vref +0.15 ?v 5v il cc input low voltage ??v dd_hv_dram_vref ?0.15 v 6v oh cc output high voltage odt enabled 2 2 termination voltage is supplied by vdd_hv_dram_vtt. v dd_hv_dram_vtt +0.81 ?v odt disabled 3 3 tie v dd_hv_dram_vtt to v ss and disable odt 0.8 v dd_hv_dram ?v 7v ol cc output low voltage odt enabled 2 ?v dd_hv_dram_vtt ?0.81 v odt disabled 3 ?0.2v dd_hv_dram v table 52. output drive current @ v dde = 2.5 v ( 200 mv) pad name drive mode minimum i oh (ma) 1 notes: 1 i oh is defined as the current sourced by the pad to drive the output to v oh . minimum i ol (ma) 2 2 i ol is defined as the current sunk by the pad to drive the output to v ol . dram acc 011 ?16.2 16.2 dram dq 011 dram clk 011
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice electrical characteristics freescale semiconductor 100 3.19.3 dram pads electrical specification (v dd_hv_dram = 1.8 v) table 53. dram pads ac elec trical specifications (v dd_hv_dram = 2.5 v) no. pad name prop. delay (ns) l ? h/h ? l 1 notes: 1 l ? h signifies low-to-high propagation delay and h ? l signifies high-to-low propagation delay. rise/fall edge (ns) drive load (pf) drive/slew rate select min max min max msb, lsb 1 dram acc 1.4/1.5 2.5/2.4 2.1/2.1 4.3/4.1 5 011 1.7/1.7 2.8/2.7 0.6/0.7 1.1/1.3 20 2 dram dq 1.4/1.5 2.5/2.4 2.1/2.1 4.3/4.1 5 011 1.7/1.7 2.8/2.7 0.6/0.7 1.1/1.3 20 3 dram clk 1.4/1.4 2.4/2.4 2.1/2.1 4.4/4.1 5 011 1.6/1.6 2.7/2.7 0.6/0.7 1.6/1.8 20 table 54. dram pads dc elec trical specifications (v dd_hv_dram = 1.8 v) no. symbol parameter condition min max unit 1v dd_hv_dram sr i/o supply voltage ?1.7 1.9v 2v dd_hv_dram_vref cc input reference voltage ? 0.49 v dd_hv_dram 0.51 v dd_hv_dram v 3v dd_hv_dram_vtt cc termination voltage 1 notes: 1 bga473: termination voltage can be supplied via package pins . bga257 termination voltage internally tied as the bga257 does not provide dram interface. disable odt ?v dd_hv_dram_vref ?0.04 v dd_hv_dram_vref +0.04 v 4v ih cc input high voltage ?v dd_hv_dram_vref + 0.125 ? v 5v il cc input low voltage ??v dd_hv_dram_vref ?0.125 v 6v oh cc output high voltage odt enabled 2 2 termination voltage is supplied by vdd_hv_dram_vtt. v dd_hv_dram_vtt +0.81 ? v odt disabled 3 3 tie v dd_hv_dram_vtt to v ss and disable odt 0.8 v dd_hv_dram ? v 7v ol cc output low voltage odt enabled 2 ?v dd_hv_dram_vtt ?0.81 v odt disabled 3 ?0.2v dd_hv_dram v
electrical characteristics mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 101 table 55. output drive current @ v dde = 1.8 v ( 100 mv) no. pad name drive mode minimum i oh (ma) 1 notes: 1 i oh is defined as the current sourced by the pad to drive the output to v oh . minimum i ol (ma) 2 2 i ol is defined as the current sunk by the pad to drive the output to v ol . 1 dram acc 000 ?3.57 3.57 001 ?7.84 7.84 010 ?5.36 5.36 110 ?13.4 13.4 2 dram dq 000 ?3.57 3.57 001 ?7.84 7.84 010 ?5.36 5.36 110 ?13.4 13.4 3 dram clk 000 ?3.57 3.57 001 ?7.84 7.84 010 ?5.36 5.36 110 ?13.4 13.4 table 56. dram pads ac elec trical specifications (v dd_hv_dram = 1.8 v) no. pad name prop. delay (ns) l ? h/h ? l 1 rise/fall edge (ns) drive load (pf) drive/slew rate select min max min max msb, lsb 1 dram acc 1.4/1.4 2.4/2.4 0.6/1.0 2.7/2.6 5 000 1.7/1.7 2.8/2.7 0.2/0.4 0.5/0.6 20 1.4/1.5 2.4/2.5 1.1/1.1 3.0/2.7 5 001 1.7/1.7 2.8/2.8 0.4/0.4 0.7/0.7 20 1.4/1.5 2.4/2.4 1.0/1.1 2.9/2.7 5 010 1.7/1.7 2.8/2.7 0.3/0.4 0.6/0.7 20 1.4/1.5 2.5/2.5 1.5/1.1 3.1/2.6 5 110 1.7/1.8 2.8/2.8 0.4/0.4 0.7/0.6 20
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice electrical characteristics freescale semiconductor 102 3.20 reset characteristics 3.20.1 reset pin characteristics 3.21 reset sequence this section shows the duration for di fferent reset sequences. it describe s the different reset sequences and it specifies the start conditions a nd the end indication for the reset se quences depending on internal or external vreg mode. 2 dram dq 1.4/1.4 2.4/2.4 0.6/1.0 2.7/2.6 5 000 1.7/1.7 2.8/2.7 0. 2/0.4 0.5/0.6 20 1.4/1.5 2.4/2.5 1.1/1.1 3.0/2.7 5 001 1.7/1.7 2.8/2.8 0.4/0.4 0.7/0.7 20 1.4/1.5 2.4/2.4 1.0/1.1 2.9/2.7 5 010 1.7/1.7 2.8/2.7 0. 3/0.4 0.6/0.7 20 1.4/1.5 2.5/2.5 1. 5/1.1 3.1/2.6 5 110 1.7/1.8 2.8/2.8 0. 4/0.4 0.7/0.6 20 3 dram clk 1.4/1.4 2.4/ 2.4 0.4/0.6 2.7/2.7 5 000 1.6/1.6 2.7/2.7 0. 7/0.9 1.8/3.4 20 1.4/1.4 2.4/2.4 1. 1/1.1 3.0/2.8 5 001 1.7/1.7 2.7/2.7 0.3/0.4 1.0/1.1 20 1.4/1.4 2.4/2.4 0. 9/1.1 3.0/2.8 5 010 1.6/1.6 2.7/2.7 0. 3/0.4 0.9/1.0 20 1.4/1.4 2.5/2.5 1. 5/1.2 3.2/2.6 5 110 1.7/1.7 2.7/2.7 0.4/0.4 1.1/1.2 20 notes: 1 l ? h signifies low-to-high propagation delay and h ? l signifies high-to-low propagation delay. table 57. reset pin characteristics no. symbol parameter conditions min max unit 1w frst sr reset pulse is sure to be filtered ??70ns 2w nfrst sr reset pulse is sure not to be filtered ? 400 ? ns table 56. dram pads ac electrical specifications (v dd_hv_dram (continued) = 1.8 v) no. pad name prop. delay (ns) l ? h/h ? l 1 rise/fall edge (ns) drive load (pf) drive/slew rate select min max min max msb, lsb
electrical characteristics mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 103 3.21.1 reset sequence duration table 58 specifies the minimum and the maximum reset sequence duration for the five different reset sequences described in section 3.21.2, reset sequence description. 3.21.2 reset sequence description the figures in this section show the internal stat es of the mpc5675k during the five different reset sequences. the doted lines in the figur es indicate the starting point and the end point for which the duration is specified in table 58 . the start point and end point conditions as well as the reset trigger mapping to the different reset sequences is specified in section 3.21.2, reset sequence description. with the beginning of drun mode, the first instruction is fetched and ex ecuted. at this point, application execution starts and the internal reset sequence is finished. the following figures show the internal states of the mpc5675k during the execution of the reset sequence and the possible states of the reset signal pin. note reset is a bidirectional pin. the voltage level on this pin can either be driven low by an external reset genera tor or by the mpc5675k internal reset circuitry. a high level on this pin can only be gene rated by an external pull up resistor which is strong enough to ove rdrive the weak internal pull down resistor. the rising edge on reset in the following figures indicates the time when the device stops driving it low. the reset sequence durations given in table 58 are applicable only if the internal reset sequence is not prolonged by an external rese t generator keeping reset asserted low beyond the last phase3. table 58. reset sequences no. symbol parameter t reset unit min typ max 1 notes: 1 the maximum value is applicable only if the reset sequence duration is not prolonged by an extended assertion of reset by an external reset generator. 1t drb cc destructive reset sequence, bist enabled 60 65 70 ms 2t dr cc destructive reset sequence, bist disabled 40 400 1000 s 3t erlb cc external reset sequence long, bist enabled 60 65 70 ms 4t frl cc functional reset sequence long 40 300 600 s 5t frs cc functional reset sequence short 1 3 10 s
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice electrical characteristics freescale semiconductor 104 figure 21. destructive reset sequence, bist enabled figure 22. destructive reset sequence, bist disabled figure 23. external reset sequence long, bist enabled phase0 phase1,2 phase3 phase1,2 phase3 drun bist reset sequence trigger reset sequence start condition reset establish flash device self mbist lbist application irc and pwr init te s t setup config flash init device config execution t drb, min < t reset < t drb, max phase0 phase1,2 phase3 drun reset sequence trigger reset sequence start condition reset establish flash device application irc and pwr init config execution t dr, min < t reset < t dr, max phase1,2 phase3 phase1,2 phase3 drun bist reset sequence trigger reset sequence start condition reset flash device self mbist lbist application init te s t setup config flash init device config execution t erlb, min < t reset < t erlb, max
electrical characteristics mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 105 figure 24. functional reset sequence long figure 25. functional reset sequence short the reset sequences shown in figure 24 and figure 25 are triggered by functi onal reset events. reset is driven low during these two reset sequences only if the corresponding functiona l reset source (which triggered the reset sequence) was enabled to drive reset low for the duration of the internal reset sequence. see the rgm_f bre register in the mpc5675k reference manual (mpc5675krm) for more information. 3.21.3 reset sequence trigger mapping the following table shows the possible trigger events for the different reset sequences, depending on the vreg mode (external or internal). it specifies the reset sequence star t conditions as well as the reset sequence end indications that are the basis for the timing data provided in table 58 . phase1,2 phase3 drun reset sequence trigger reset sequence start condition reset application flash init device config execution t frl, min < t reset < t frl, max phase3 drun reset sequence trigger reset sequence start condition reset application execution t frs, min < t reset < t frs, max
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice electrical characteristics freescale semiconductor 106 table 59. reset sequence trigger?reset sequence reset sequence trigger vreg mode 1 notes: 1 vreg mode: i = internal vreg mode, e = external vreg mode. reset sequence start condition reset sequence end indication reset sequence destructive reset sequence, bist enabled 2 2 whether bist is executed or not depends on device conf iguration data stored in the shadow sector of the nvm. destructive reset sequence, bist disabled 2 external reset sequence long, bist enabled functional reset sequence long functional reset sequence short all active internal destructive reset sources (lvds or internal hvd during power-up and during operation) i section 3. 21.4.1, internal vreg mode release of reset 3 3 end of the internal reset sequence (as specified in table 58 ) can only be observed by release of reset if it is not held low externally beyond the end of the in ternal sequence which would prolong t he internal reset phase3 until reset is released externally. triggers cannot trigger cannot trigger cannot trigger e section 3. 21.4.2, external vreg mode cannot trigger cannot trigger cannot trigger assertion of reset_sup 4 4 in external vreg mode only. assertion of reset 5 5 the assertion of reset can only trigger a reset sequenc e if the device was running (reset released) before. reset does not gate a destructive reset sequence, bist enabled or a destructive reset sequence, bist disabled . however, it can prolong these sequences if reset is held low externally beyond the end of the internal sequence (beyond phase3). i/e section 3. 21.4.3, external reset via reset cannot trigger triggers 6 6 if reset is configured for long reset (default) and if bist is enabled via device configuration data stored in the shadow sector of the nvm. triggers 7 triggers 8 all internal functional reset sources configured for long reset i/e sequence starts with internal reset trigger release of reset 9 cannot trigger cannot trigger triggers cannot trigger all internal functional reset sources configured for short reset i/e cannot trigger cannot trigger cannot trigger triggers
electrical characteristics mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 107 3.21.4 reset sequence?start condition the impact of the voltage thresholds on the startin g point of the internal reset sequence are becoming important if the voltage rails / signa ls ramp up with a very slow slew rate compared to the overall reset sequence duration. 3.21.4.1 internal vreg mode figure 26 shows the voltage threshold that determines the start of the destructive reset sequence, bist enabled and the start for the destructive reset seque nce, bist disabled . the last voltage rail crossing the levels shown in figure 26 determines the start of the reset times specified in table 58 . figure 26. reset sequence start in internal vreg mode 3.21.4.2 external vreg mode figure 27 and figure 28 show the voltage thresholds that dete rmine the start of the destructive reset sequence, bist enabled and the start for the destructive reset sequence, bist disabled. note reset_sup must not be released unless v dd_lv_ xxx is within its valid range of operation. 7 if reset is configured for long reset (default) and if bist is disabled via device configuration data stored in the shadow sector of the nvm. 8 if reset is configured for short reset. 9 internal reset sequence can only be observed by state of reset if bidirectional reset functionality is enabled for the functional reset source which triggered the reset sequence. table 60. voltage thresholds variable name value v min lvdreg ? 3.5% v max lvdreg + 3.5% supply rail vdd_hv_pmu vdd_hv_io vdd_hv_flash vdd_hv_adv v max supply rail v min v t t reset, min starts here t reset, max starts here
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice electrical characteristics freescale semiconductor 108 figure 27. external vreg mode, reset_sup rises after v dd_hv_ xxx are stable figure 28. external vreg mode, reset_sup rises with v dd_hv_ xxx note in case reset_sup has reached a valid high level before v dd_hv_io is stable, the reset sequence will start as documented in figure 28 as the reset_sup input circuitry needs a valid v dd_hv_io rail in order to detect a high level on reset_sup . vdd_hv_pmu v t 0.8 vdd_hv_io reset_sup v t t reset, min starts here t reset, max starts here vdd_hv_io vdd_hv_flash vdd_hv_adv 0.2 vdd_hv_io vdd_hv_pmu v t lvdreg + 3.5% reset_sup v t t reset, min starts here t reset, max starts here vdd_hv_io vdd_hv_flash vdd_hv_adv lvdreg ? 3.5%
electrical characteristics mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 109 3.21.4.3 external reset via reset figure 29 shows the voltage thresholds that determine th e start of the reset sequences initiated by the assertion of reset as specified in table 59 . figure 29. reset seque nce start via reset assertion 3.21.5 external w atchdog window if the application design requi res the use of an external watchdog the data provided in section 3.21, reset sequence, can be used to determine the correct posit ioning of the trigger window for the external watchdog. figure 30 shows the relationships be tween the minimum and the ma ximum duration of a given reset sequence and the position of an external watchdog trigger window. figure 30. reset sequence?external watchdog trigger window position 0.65 vdd_hv_io reset_sup v t t reset, min starts here t reset, max starts here 0.352 vdd_hv_io internal reset sequence start condition (signal or voltage rail) earliest application start latest application start application time required to prepare watchdog trigger t wdstart, min t wdstart, max t reset, min t reset, max watchdog needs to be triggered within this window external watchdog window open external watchdog window open external watchdog window closed basic application init basic application init application running application running watchdog trigger external watchdog window closed
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice electrical characteristics freescale semiconductor 110 3.22 peripheral timing characteristics 3.22.1 sdram (ddr) the mpc5675k memory controller suppor ts three types of ddr devices: ? ddr-1 (sstl_2 class ii interface) ? ddr-2 (sstl_18 interface) ? lpddr/mobile-ddr (1.8v i/o supply voltage) jedec standards define the mi nimum set of requirements for compliant memory devices: ? jedec standard, ddr2 sdram spec ification, jesd79-2c, may 2006 ? jedec standard, double data rate (d dr) sdram specificat ion, jesd79e, may 2005 ? jedec standard, low power double data rate (lpddr) sdram specification, jesd79-4, may 2006 the mpc5675k supports the confi guration of two output drive st rengths for ddr2 and lpddr: ? full drive strength ? half drive strength (intended for lighter loads or point-to-point environments) the mpc5675k memory controller supports dynamic on- die termination in the host device and in the ddr2 memory device. this section includes ac specificati ons for all ddr sdram pins. the dc parameters are specified in the section 3.19, dram pad specifications. 3.22.1.1 ddr and ddr2 sdram ac timing specifications table 61. ddr and ddr2 (ddr2- 400) sdram timing specifications at recommended operatin g conditions with v dd_mem_io of ? 5% no. symbol parameter min max unit 1 t ck cc clock cycle time, cl = x ?90mhz 2 v ix-ac cc mck ac differential crosspoint voltage 1 v dd_mem_io 0.5 ?0.1 v dd_mem_io 0.5 +0.1 v 3 t ch cc ck high pulse width 1, 2 0.47 0.53 t ck 4 t cl cc ck low pulse width 1, 2 0.47 0.53 t ck 5 t dqss cc skew between mck and dqs transitions 2, 3 ? 0.25 0.25 t ck 8 t os(base) cc address and control output setup time relative to mck rising edge 2, 3 (t ck /2 ? 750) ps 9 t oh(base) cc address and control output hold time relative to mck rising edge 2, 3 (t ck /2 ? 750) ? ps 11 t ds1(base) cc dq and dm output setup time relative to dqs 2, 3 (t ck /4 ? 500) ? ps 12 t dh1(base) cc dq and dm output hold time relative to dqs 2, 3 (t ck /4 ? 500) ? ps
electrical characteristics mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 111 figure 31 shows the ddr sdram write timing. figure 31. ddr write timing figure 32 and figure 33 show the ddr sdram read timing. figure 32. ddr read timing, dq vs. dqs 14 t dqsq cc dqs-dq skew for dqs and associated dq inputs 2 ?(t ck /4 ? 600) (t ck /4?600) ps 15 t dqsen cc dqs window start position related to cas read command 1, 2, 3, 4, 5 tbd tbd ps notes: 1 measured with clock pin loaded with diff erential 100 ohm termination resistor. 2 all transitions measured at mid-supply ( v dd_mem_io /2). 3 measured with all outputs except the clock loaded with 50 ohm termination resistor to v dd_mem_io /2. 4 in this window, the first rising edge of dqs should o ccur. from the start of the window to dqs rising edge, dqs should be low. 5 window position is given for t dqsen = 2.0 t ck . for other values of t dqsen , window position is shifted accordingly. table 61. ddr and ddr2 (ddr2-400) sdram timing specifi cations (continued) at recommended operatin g conditions with v dd_mem_io of ? 5% no. symbol parameter min max unit mck t ch t cl dqs t dqss dq, dm (out) t ds t dh t ck dqs (in) any dq (in) t dqsq t dqsq
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice electrical characteristics freescale semiconductor 112 figure 33. ddr read timing, dqsen figure 34 provides the ac test load for the ddr bus. figure 34. ddr ac test load 3.22.2 ieee 1149.1 (jtag) interface timing table 62. jtag pin ac electrical characteristics no. symbol parameter conditions min max unit 1t jcyc d tck cycle time 1 ?100?ns 2t jdc d tck clock pulse width (measured at v dde /2) ? 40 60 ns 3t tckrise d tck rise and fall times (40%?70%) ? ? 3 ns 4t tmss, t tdis d tms, tdi data setup time ? 5 ? ns 5t tmsh, t tdih d tms, tdi data hold time ? 25 ? ns 6t tdov d tck low to tdo data valid ? ? 20 ns 7t tdoi d tck low to tdo data invalid ? 0 ? ns 8t tdohz d tck low to tdo high impedance ? ? 20 ns 11 t bsdv d tck falling edge to output valid ? ? 50 ns 12 t bsdvz d tck falling edge to output valid out of high impedance ? ? 50 ns 13 t bsdhz d tck falling edge to output high impedance ? ? 50 ns 14 t bsdst d boundary scan input valid to tck rising edge ? 50 ? ns 15 t bsdht d tck rising edge to boundary scan input invalid ? 50 ? ns mck dqs (in) t os t oh command address read t dqsen (min) t dqsen output z 0 =50 ? r l = 50 ? v dd_mem_io /2
electrical characteristics mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 113 figure 35. jtag test clock input timing figure 36. jtag test access port timing notes: 1 f tck =1/t tck . f tck needs to be smaller than or equal to the system clock (sys_clk). tck 1 2 2 3 3 tck 4 5 6 7 8 tms, tdi tdo
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice electrical characteristics freescale semiconductor 114 figure 37. jtag boundary scan timing 3.22.3 nexus timing table 63. nexus debug port timing 1 no. symbol parameter conditions min max unit 1t mcko cc mcko cycle time ?15.75?ns 2t mdc cc mcko duty cycle ?3366% 3t mdov cc mcko low to mdo, mseo , evto data valid 2 ?(?0.1)t mcko (0.2)t mcko ns 4t evtipw cc evti pulse width ?4.0?t tcyc 5t evtopw cc evto pulse width ?1?t mcyc 6t tcyc cc tck cycle time 3 ?60?ns 7t tdc cc tck duty cycle ?4060% 8t ntdis, t ntmss cc tdi, tms data setup time ?12?ns 9t ntdih, t ntmsh cc tdi, tms data hold time ?6?ns 10 t jov cc tck low to tdo data valid ?018ns 11 t joiv cc tck low to tdo data invalid ?6?ns tck output signals input signals output signals 11 12 13 14 15
electrical characteristics mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 115 figure 38. nexus output timing 3.22.4 external interrupt timing (irq pins) notes: 1 jtag specifications in this table apply when used for deb ug functionality. all nexus ti ming relative to mcko is measured from 50% of mcko and 50% of the respective signal. 2 mdo, mseo , and evto data is held valid until next mcko low cycle. 3 the system clock frequency needs to be three times faster than the tck frequency. table 64. external interr upt timing (nmi irq) no. symbol parameter conditions min max unit 1t ipwl sr irq pulse width low ?tbd?ns 2t ipwh sr irq pulse width high ?tbd?ns 3t icyc sr irq edge to edge time 1 notes: 1 applies when irq pins are configured for ri sing edge or falling edge events, but not both. ?tbd?ns table 65. external interrupt timing (gpio irq) no. symbol parameter conditions min max unit 1t ipwl sr irq pulse width low ?tbd?ns 2t ipwh sr irq pulse width high ?tbd?ns 3t icyc sr irq edge to edge time 1 notes: 1 applies when irq pins are configured for ri sing edge or falling edge events, but not both. ?tbd?ns 1 2 mcko mdo mseo evto output data valid 3 evti 4 5
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice electrical characteristics freescale semiconductor 116 figure 39. external interrupt timing 3.22.5 flexcan timing 3.22.6 dspi timing table 66. flexcan timing no. symbol parameter conditions min max unit 1f can_tx cc flexcan design target transmit data rate ?10?mbit/s 2f can_rx cc flexcan design target receive data rate ?10?mbit/s table 67. dspi timing no. symbol parameter conditions min max unit 1t sck cc dspi cycle time master (mtfe = 0) 62 ? ns slave (mtfe = 0) 62 ? slave receive only mode 1 16 ? 2t csc cc pcs to sck delay ?16?ns 3t asc cc after sck delay ?16?ns 4t sdc cc sck duty cycle ?0.4t sck 0.6 t sck ns 5t a cc slave access time ss active to sout valid ? 40 ns 6t dis cc slave sout disable time ss inactive to sout high-z or invalid ? 10 ns 7t pcsc cc pcsx to pcss time ?13?ns 8t pasc cc pcss to pcs x time ?13?ns clkout irq 1 2 3
electrical characteristics mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 117 9t sui cc data setup time for inputs master (mtfe = 0) 20 ? ns slave 2? master (mtfe = 1, cpha = 0) 5? master (mtfe = 1, cpha = 1) 20 ? 10 t hi cc data hold time for inputs master (mtfe = 0) ?5 ? ns slave 4? master (mtfe = 1, cpha = 0) 11 ? master (mtfe = 1, cpha = 1) ?5 ? 11 t suo cc data valid (after sck edge) master (mtfe = 0) ?4ns slave ?23 master (mtfe = 1, cpha = 0) ?11 master (mtfe = 1, cpha = 1) ?5 12 t ho cc data hold time for outputs master (mtfe = 0) ?2 ? ns slave 6? master (mtfe = 1, cpha = 0) 6? master (mtfe = 1, cpha = 1) ?2 ? 13 t dt cc delay after transfer (minimum cs negation time) continuous mode non-continuos mode 2 62 134 ? ? ns notes: 1 slave receive only mode can operate at a maximum frequen cy of 60 mhz. note that in this mode, the dspi can receive data on sin, but no valid data is transmitted on sout. 2 in non-continuous mode, this value is always t sck dspi_ctar n [dt] dspi_ctar n [pdt]. the minimum permissible value of dt is 2 and the minimum permissibl e value of pdt is 1. see the dspi chapter of the mpc5675k reference manual (mpc5675krm) for more information. table 67. dspi timing (continued) no. symbol parameter conditions min max unit
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice electrical characteristics freescale semiconductor 118 figure 40. dspi classic spi timing?master, cpha = 0 figure 41. dspi classic spi timing?master, cpha = 1 data last data first data first data data last data sin sout pcsx sck output 4 9 12 1 11 10 4 sck output (cpol=0) (cpol=1) 3 2 data last data first data sin sout 12 11 10 last data data first data sck output sck output pcsx 9 (cpol=0) (cpol=1)
electrical characteristics mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 119 figure 42. dspi classic spi timing?slave, cpha = 0 figure 43. dspi classic spi timing?slave, cpha = 1 last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 12 sck input first data last data sck input 2 (cpol=0) (cpol=1) 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol=0) (cpol=1)
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice electrical characteristics freescale semiconductor 120 figure 44. dspi modified transfer format timing?master, cpha = 0 figure 45. dspi modified transfer format timing?master, cpha = 1 pcsx 3 1 4 10 4 9 12 11 sck output sck output sin sout first data data last data first data data last data 2 (cpol=0) (cpol=1) pcsx 10 9 12 11 sck output sck output sin sout first data data last data first data data last data (cpol=0) (cpol=1)
electrical characteristics mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 121 figure 46. dspi modified transfer format timing?slave, cpha = 0 figure 47. dspi modified transfer format timing?slave, cpha = 1 last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 sck input first data last data sck input 2 (cpol=0) (cpol=1) 12 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol=0) (cpol=1)
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice electrical characteristics freescale semiconductor 122 figure 48. example of non-conti nuous format (cpha = 1, cont = 0) figure 49. example of continuous transfer (cpha = 1, cont = 1) figure 50. dspi pcs strobe (pcss ) timing 3.22.7 pdi timing table 68. pdi electrical characteristics no. symbol parameter conditions min max unit 1t pdi_clock sr pdi clock period ?15?ns sck pcsx sck master sout master sin (cpol = 0) (cpol = 1) 2 2 3 13 sck pcs sck master sout master sin (cpol = 0) (cpol = 1) (cpol = 0) sck 3 2 2 pcsx 7 8 pcss
electrical characteristics mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 123 3.22.8 fast ethernet interface mii signals use cmos signal levels compatible with devices operating at either 5.0 v or 3.3 v. signals are not ttl compatible. they follow the cmos electrical characteristics. 3.22.8.1 mii receive signal timing (r xd[3:0], rx_dv, rx_er, and rx_clk) the receiver functions correctly up to a rx_clk maximum fr equency of 25 mhz +1%. there is no minimum frequency requirement. in addition, the syst em clock frequency must exceed four times the rx_clk frequency. 2t pdi_is sr input setup time 1 ?3?ns 3t pdi_ih sr input hold time 1 ?3?ns notes: 1 data can be captured at both launching and capturing edge of pdi_clk. pdi timing table 69. mii receive signal timing no. parameter min max unit 1 rxd[3:0], rx_dv, rx_er to rx_clk setup 5? ns 2 rx_clk to rxd[3:0], rx_dv, rx_er hold 5? ns 3 rx_clk pulse width high 40% 60% rx_clk period 4 rx_clk pulse width low 40% 60% rx_clk period table 68. pdi electrical characteristics (continued) no. symbol parameter conditions min max unit pdi_clock 2 3 pdi_data[15:0] input data valid pdi_line_v pdi_frame_v 1
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice electrical characteristics freescale semiconductor 124 figure 51. mii receive signal timing diagram 3.22.8.2 mii transmit signal timing (txd[3:0], tx_en, tx_er, tx_clk) the transmitter functions correctly up to a tx_c lk maximum frequency of 25 mhz +1%. there is no minimum frequency requirement. in addition, the syst em clock frequency must exceed four times the tx_clk frequency. the transmit outputs (txd[3:0], tx_en, tx_er) can be programmed to transiti on from either the rising or falling edge of tx_clk, and the timing is the same in either case. this options allows the use of non-compliant mii phys. refer to the ethernet chapter for detail s of this option and how to enable it. figure 52. mii transmit signal timing diagram table 70. mii transmit signal timing 1 notes: 1 output pads configured with src = 0b11. no. parameter min max unit 5 tx_clk to txd[3:0], tx_en, tx_er invalid 5? ns 6 tx_clk to txd[3:0], tx_en, tx_er valid ?25 ns 7 tx_clk pulse width high 40% 60% tx_clk period 8 tx_clk pulse width low 40% 60% tx_clk period 1 2 rx_clk (input) rxd[3:0] (inputs) rx_dv rx_er 3 4 6 tx_clk (input) txd[3:0] (outputs) tx_en tx_er 5 7 8
electrical characteristics mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 125 3.22.8.3 mii async inputs sign al timing (crs and col) figure 53. mii async inputs timing diagram 3.22.8.4 mii serial management channel timing (mdio and mdc) the fec functions correctly with a maximum mdc fre quency of 5 mhz. table 71. mii async inputs signal timing 1 notes: 1 output pads configured with src = 0b11. no. parameter min max unit 9 crs, col minimum pulse width 1.5 ? tx_clk period table 72. mii serial management channel timing 1 notes: 1 output pads configured with src = 0b11. no. parameter min max unit 10 mdc falling edge to mdio output invalid (minimum propagation delay) 0? ns 11 mdc falling edge to mdio output valid (max prop delay) ?25 ns 12 mdio (input) to mdc rising edge setup 10 ? ns 13 mdio (input) to mdc rising edge hold 0? ns 14 mdc pulse width high 40% 60% mdc period 15 mdc pulse width low 40% 60% mdc period crs, col 9
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice electrical characteristics freescale semiconductor 126 figure 54. mii serial management channel timing diagram 3.22.9 external bus interface (ebi) timing table 73. ebi timing no. symbol parameter 45 mhz (ext. bus freq) 1 unit notes min max 1 t c cc d_clkout period 22.2 ? ns signals are measured at 50% v dde . 2 t cdc cc d_clkout duty cycle 45% 55% t c ? 3 t crt cc d_clkout rise time ??ns ? 4 t cft cc d_clkout fall time ??ns ? 5 t coh cc d_clkout posedge to output signal invalid or high z (hold time) d_add[9:30] d_bdip d_cs[0:3] d_dat[0:15] d_oe d_rd_wr d_ta d_ts d_we [0:3]/d_be [0:3] 1.0 ? ns ? 11 mdc (output) mdio (output) 12 13 mdio (input) 10 14 15
electrical characteristics mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 127 6 t cov cc d_clkout posedge to output signal valid (output delay) d_add[9:30] d_bdip d_cs[0:3] d_dat[0:15] d_oe d_rd_wr d_ta d_ts d_we [0:3]/d_be [0:3] ?10ns ? 7 t cis cc input signal valid to d_clkout posedge (setup time) d_add[9:30] d_dat[0:15] d_rd_wr d_ta d_ts 7.5 ? ns ? 8 t cih cc d_clkout posedge to input signal invalid (hold time) d_add[9:30] d_dat[0:15] d_rd_wr d_ta d_ts 1.0 ? ns ? 9 t apw cc d_ale pulse width 6.5 ? ns the timing is for asynchronous external memory system. 10 t aai cc d_ale negated to address invalid 1.5 ? ns the timing is for asynchronous external memory system. ale is measured at 50% of vdde. notes: 1 speed is the nominal maximum frequency. maximum core speed allowed is 180 mhz plus frequency modulation (fm). table 73. ebi timing (continued) no. symbol parameter 45 mhz (ext. bus freq) 1 unit notes min max
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice electrical characteristics freescale semiconductor 128 figure 55. d_clkout timing figure 56. synchronous output timing 1 2 2 3 4 d_clkout v dde / 2 v ol_f v oh_f 6 5 5 d_clkout bus 5 output signal output v dde / 2 v dde / 2 v dde / 2 6 5 output signal v dde / 2 6
electrical characteristics mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 129 figure 57. synchronous input timing figure 58. ale signal timing 7 8 d_clkout input bus 7 8 input signal v dde / 2 v dde / 2 v dde / 2 ipg_clk d_clkout d_ale d_ts addr data d_add/d_dat 9 10
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice electrical characteristics freescale semiconductor 130 3.22.10 i 2 c timing table 74. i 2 c scl and sda input timing specifications no. symbol parameter value unit min max 1 ? d start condition ho ld time 2 ? ip bus cycle 1 notes: 1 inter peripheral clock is the clock at which the i 2 c peripheral is working in the device. 2 ? d clock low time 8 ? ip bus cycle 1 4 ? d data hold time 0.0 ? ns 6 ? d clock high time 4 ? ip bus cycle 1 7 ? d data setup time 0.0 ? ns 8 ? d start condition setup time (for re peated start condition only) 2 ? ip bus cycle 1 9 ? d stop condition setup time 2 ? ip bus cycle 1 table 75. i 2 c scl and sda output timing specifications no. symbol parameter value unit min max 1 1 notes: 1 programming ibfd (i 2 c bus frequency divider) with the maximum frequency results in the minimum output timings listed. the i 2 c interface is designed to scale the data transition time, moving it to the middle of the scl low period. the actual position is affected by the presca le and division values programmed in ifdr. ? d start condition hold time 6 ? ip bus cycle 2 2 inter peripheral clock is the clock at which the i 2 c peripheral is working in the device. 2 1 ? d clock low time 10 ? ip bus cycle 1 3 3 3 because scl and sda are open-drain-type outputs, which the processor can only actively drive low, the time scl or sda takes to reach a high level depends on external signal capacitance and pull-up resistor values. ? d scl/sda rise time ? 99.6 ns 4 1 ? d data hold time 7 ? ip bus cycle 1 5 1 ? d scl/sda fall time ? 99.5 ns 6 1 ? d clock high time 10 ? ip bus cycle 1 7 1 ? d data setup time 2 ? ip bus cycle 1 8 1 ? d start condition setup time (for repeated start condition only) 20 ? ip bus cycle 1 9 1 ? d stop condition setup time 10 ? ip bus cycle 1
electrical characteristics mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 131 figure 59. i 2 c input/output timing 3.22.11 linflex timing the maximum bit rate is 1.875 mbit/s. scl sda 1 2 3 4 5 6 7 8 9
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice package characteristics freescale semiconductor 132 4 package characteristics 4.1 package mechanical data 4.1.1 257 mapbga figure 60. 257 mapbga mechanical data (1 of 2)
package characteristics mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 133 figure 61. 257 mapbga mechanical data (2 of 2)
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice package characteristics freescale semiconductor 134 4.1.2 473 mapbga figure 62. 473 mapbga package mechanical data (1 of 3)
package characteristics mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 135 figure 63. 473 mapbga package mechanical data (2 of 3)
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice package characteristics freescale semiconductor 136 figure 64. 473 mapbga package mechanical data (3 of 3)
orderable parts mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 137 5 orderable parts 6 reference documents 1. nexus (ieee-isto 5001??2008) 2. measurement of emission of ics?iec 61967-2 3. measurement of emission of ics?iec 61967-4 4. measurement of imm unity of ics?iec 62132-4 5. semiconductor equipment a nd materials international 3081 zanker road san jose, ca 95134 usa (408) 943-6900 6. jedec specifications are avai lable at http://www.jedec.org table 76. orderable part number summary part number flash/sram package speed (mhz) ppc5675kfmmsj 2 mb/512 kb 473 mapbga (pb free) 180 ppc5675kfmmmj 2 mb/512 kb 257 mapbga (pb free) 180 ppc5674kmmsj 1.5 mb/384 kb 473 mapbga (pb free) 180 ppc5674kmmmj 1.5 mb/384 kb 257 mapbga (pb free) 180 ppc5673kmmsj 1 mb/256 kb 473 mapbga (pb free) 150 ppc5673kfmmmj 1 mb/256 kb 257 mapbga (pb free) 150 mpc f note: not all options are available on all devices. see ta b l e 7 6 . 5675k qualification status core code device number device feature set device revision temperature range v = ?40 c to 105 c device revision f0 = fab and mask operating frequency 1 = 150 mhz tape and reel status r = tape and reel (blank) = trays qualification status p = pre-qualification m = fully spec. qualified, general market flow s = fully spec. qualified, automotive flow f0 m temperature range mm package identifier 3 r operating frequency tape and reel status device feature set f=flexray package identifier mm = 257 bga 2 = 180 mhz 3 = 220 mhz m = ?40 c to 125 c ms= 473 bga (ambient)
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice document revision history freescale semiconductor 138 7. mil-spec and eia/jesd (jedec ) specifications are availa ble from global engineering documents at 800-854-7179 or 303-397-7956. 8. c.e. triplett and b. joiner, ?an experiment al characterization of a 272 pbga within an automotive engine controller module,? pr oceedings of semitherm, san diego, 1998, pp. 47?54. 9. g. kromann, s. shidore, and s. addison, ?t hermal modeling of a pbga for air-cooled applications,? electr onic packaging and production, pp. 53?58, march 1998. 10. b. joiner and v. adams, ?measurement and si mulation of junction to bo ard thermal resistance and its application in thermal modeling,? pr oceedings of semither m, san diego, 1999, pp. 212?220. 7 document revision history table 77 summarizes revisions to this document. table 77. revision history revision date description of changes 1 6 oct 2009 initial release. 2 6 dec 2009 updated ball map tables, pin mux tabl es, supply and system pin tables. added pmc specifications. 3 2 jul 2010 updated ball map tables, pin mux tabl es, supply and system pin tables. updated pad specifications. added reset specifications section. 430 apr 2011 removed thickness dimension from package diagrams on cover page. added footnote ?do not connect pin directly to a power supply or ground? for mdo[0:15] and mseo[0:1] pins to ta b l e 9 and ta b l e 1 0 . in ta bl e 1 7 , pmc electrical specifications : ? added mininum and maximum slew rate specifications for lvdreg. ? removed lvdc minimum and maximum hysteresis specifications ? removed hvdc minimum and maximum hysteresis specifications ? corrected hvcd nominal hysreresis from 1.32 to 1.36 in ta bl e 1 8 , updated specifications for device q (fet). renamed ta b l e 1 9 to ?current consumption characteristics.? in ta bl e 1 9 , updated adc current consumption to 1.2 ma per adc plus 0.7 ma (2.0 ma total) for adc0. ? removed ?typical? figures for these specifications. ? added footnote ?adc0 includes 0.7 ma di ssipation for the temperature sensor (tsens).? updated accuracy specification in ta bl e 2 0 , temperature sensor electrical characteristics : changed ?t j = ?40 c to t a = 25 c? to ?t j = ?40 c to t a = 125 c,? removed row ?t j = t a to 125 c?. in ta bl e 2 1 , main oscillator electrical characteristics , added symbol name f xoschs for oscillator frequency specification. renamed section 3.9, ?power dissipat ion and current consumption,? to section 3.9, supply current characteristics . in ta b l e 2 3 , rc oscillator electrical characteristics : ? added specification ? irctrim ? internal rc oscillator trimming step.? ? removed specification ? rctrim ? post trim accuracy: the va riation of the ptf from the 16 mhz? (specification replaced by ? irctrim ? internal rc oscillato r trimming step?).
document revision history mpc5675k microcontrolle r data sheet, rev. 4 preliminary?subject to change without notice freescale semiconductor 139 430 apr 2011 in table 24, adc conversion characteristics, updated gain error (gne) to ?min = ?4 max = +4 lsb? . added ta bl e 3 0 , code flash write access timing, and ta b l e 3 1 , data flash write access timing. table 77. revision history (continued) revision date description of changes
mpc5675k microcontroller data sheet, rev. 4 preliminary?subject to change without notice document revision history freescale semiconductor 140 how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com document number: mpc5675k rev. 4 may 5, 2011 11:16 am information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freesc ale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2011. all rights reserved.

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